Klaus2m5 wrote:
Shouldn't this be a 32k RAM?
creoguy wrote:
My understanding of Chris's design is that the 32k SRAM is divided up so half is for the OS, and then the other half is for the ACIA, VIA and the remainder for use as potential I/O space in a future revision.
The RAM is a 32K chip, but half of the capacity is deliberately unused. That's to simplify the glue logic, I assume.
Basically, the /OE input of the RAM is used as an extra /CS input, and it's driven from address line A14. Of course placing /OE high doesn't really de-select the chip, but it prevents a read from taking control of the data bus -- and that's sufficient. The chip becomes a Write Only Memory anytime A14 is high. That includes $4000-7FFF, which is where I/O appears.
ETA: the same "/OE as an additional /CE" trick is used in Garth's
very basic whole-computer schematic. In fact all the glue for memory/I-O is pretty much identical, except Garths' "whole computer in one diagram" design has no ACIA, just a VIA.
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