Thanks for the article.

Definitely something to keep in the back of your head when working with casex.

Out of interest I have done Googling and also found other web sites mentioning casex can cause issues on initialisation, but none of them give any real concrete examples.

I would like to hear from other people reading that had some bad experiences using casex.

Hi All!

I managed to Squeeze one more post in this series before the turn of 2017!

Here is the link:

http://c64onfpga.blogspot.co.za/2017/12 ... -fpga.html

Enjoy and have a wonderful 2018!

Just released my next post:

http://c64onfpga.blogspot.co.za/2018/01 ... sdram.html

Just released my next post:

http://c64onfpga.blogspot.co.za/2018/01 ... sdram.html

In this post we explore how to access write to SDRAM from an FPGA core.

I have just released the next post in the series. In this post we develop the VIC-II core.

Here is the link:

http://c64onfpga.blogspot.co.za/2018/01 ... -core.html

I have just published my next post in my series of developing a C64 on an FPGA.

In this post we add the VIC-II core to our C64 boot simulation, and see if it renders the welcome screen correctly.

Here is the link:

http://c64onfpga.blogspot.com/2018/02/i ... -core.html

Interesting posts. How do you plan to get PAL raster effects to work on VGA?

@kakemons: My plan is to write the rgb output of the VIC module to SDRAM. The VGA module, which still needs to be developed, will then read the same contents back from SDRAM and generate the signal.

In effect the frames stored in SDRAM will contain the raster effects which the VGA module will render with a more or lesser amount of tearing because the VIC-II and VGA module will work at different refresh ferquencies

I have just released the next part in my series on creating a C64 implementation on an FPGA. In this post I talk about the brick wall I ran into into in using a Block RAM in dual port mode that was needed so that the 6502 and VIC-II can simultaneously can access memory.

http://c64onfpga.blogspot.co.za/2018/03 ... ggles.html

I have just released the next post in my Blog series on creating a C64 on an FPGA. In this post we manage to write the output from our VIC-II module to the SDRAM on the Zybo, but with some distortion...

In this post we will try and generate VGA signals from our FPGA. The glitch I with ended off in the previous post appeared not be a big issue at all, which I will briefly talk about in this post.

Here is the link:

http://c64onfpga.blogspot.co.za/2018/04 ... utput.html

I have just released part in my series of creating a C64 on an FPGA.

In this post we will be splitting our VGA design into two clock domains: AXI Clock domain and VGA pixel clock domain.

The above mentioned cross Clock domains is probably the part I worry the most in the whole design of reading frames from SDRAM and displaying it on on a VGA screen.

So, in this post we will see if we can cross this stormy bridge

Here is the link:

http://c64onfpga.blogspot.co.za/2018/04 ... clock.html

I have just released my next post my Blog series of creating a C64 on an FPGA.

In this post we explore reading from SDRAM with AXI.

We also do some elemetary Read Bandwidth checks. This checks is essential for a future post to determine if we can read frame data from SDRAM fast enough for display on a VGA screen.

Here is the link:

http://c64onfpga.blogspot.com/2018/05/r ... sdram.html

I have just released the next post in my series on creating a C64 on an FPGA with the Zybo Board. In this post we attempt to display a frame from SDRAM to the VGA.

Here is the link:

http://c64onfpga.blogspot.com/2018/06/dddd.html

Hi All

It has been quite while since I posted an update in this thread on my progress with this project.

I have actually been making some good progress and this module can currently boot the C64 and display on the VGA screen. You can also play a game and use an USB keyboard to interact with the C64 module.

Here is my latest post:
https://c64onfpga.blogspot.com/2019/11/implementing-sound-part-2.html