Hello all,
with this post I’d like to talk through my design and ask you guys for advice and suggestions.
As I’m developing and prototyping MARC-3, I decided to follow Daryl Rictor’s “SBC-4 Plus” design and Garth Wilson’s “Expansion Buses and Interfaces” primer and won’t go with the processor's own buses off the board.
http://sbc.rictor.org/sbc4.htmlhttp://wilsonminesco.com/6502primer/ExpBusIntrfc.htmlI’ll put CPU, RAM, CPLD, ROM emulator and an expansion port on one board. The CPLD and two 74HCT245’s will buffer all signals on the expansion port. I hope this will result in more speed and stability.
Here is the schematic of the main board:
Attachment:
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I’ll try to describe the functions of the major components is some more detail:
ATmega1284P:Connects to A0..A13 (to directly access 16KiB), D0..D7 and the RAM control signals. It will feed the system CLOCK signal to the CPLD, which will be divided by 2 to provide a strong and symmetrical PHI2 signal. It will also provide a debounced active low N_RESET signal to the CPLD. Those two last signals are connected to the common CPLD clock and tristate inputs. The reset button input and the one free I/O pin are connected to a solder pad, they are the serial communication pins of the AVR. There’s a reset button on the board, but also pads to connect to a separate button on the computer case.
During RESET, the ATmega1284P holds the N_RESET line low while it copies the desired program(s) to RAM. Once done, it becomes transparent and releases N_RESET and the 65816 starts executing instructions from RAM.
XC9572-7PC84C & WDC65C816S:All CPU pins are connected to the CPLD, except for the ones I don’t intend to use: VPB, E, MX, MLB and ABORTB. These are routed from the CPU to the CPLD pins but separated by a jumper. So I can either connect them or use the CPLD pins as spares for other purposes. The CPLD is also connected to A16..A18, N_MEMWR, N_MEMRD, RAMCS0 and RAMCS1..RAMCS3 solder pads to provide a maximum of 2MiB RAM.
The CPLD provides the following functions:
System clock generator / divider.
• A maximum of 2MiB address decoding through four RAM chip selects and 19 address lines using the upper address lines provided by the 65816’s data lines during PHI2 is low.
• Memory read write qualification with PHI2.
• Reset / tristate circuit.
• IRQ and NMI handler.
• I/O chip selects.
• VDA VPA address qualification.
During RESET, the CPLD holds the RESB and BE lines low, so that the CPU is transparent. All other I/O devices are also deactivated. The RAM chip selects are set to “111Z”, so that only the first SRAM chip is accessible by the AVR. The address lines A18..A0 are set to 000 11ZZ ZZZZ ZZZZ ZZZZ. That way the AVR is able to copy the program(s) to RAM from $00C000 - $00FFFF. After the AVR releases N_RESET, the CPLD does its normal business.
AS6C4008:This is a 512KiB 55ns SRAM. A0..A13 are connected to CPLD, CPU and AVR. A14 and A15 are connected to CPLD and CPU. A16..A18 are only connected to the CPLD. Initially there’s a single 512KiB SRAM chip. The RAM is expandable by piggybacking additional SRAM chips and tying their chip selects (RAMCS1..RAMCS3 solder pads near the RAM chip) to the CPLD accordingly.
EXPANSION PORT:Is a 50 pin IDC header which connect CPU pins buffered through two 74HC245’s: BPHI2, BRWB, BRESB, BA0..BA4 and BD0..BD7. Also N_MEMWR and N_MEMRD are provided. All remaining unused CPLD pins which will serve as chip selects, IRQ inputs etc. for I/O devices. There are several remaining pins on the header which will be connected to GND and VCC. I hope these arrangements will be adequate for a decent expansion port and will result in better performance.
A few of my questions are:
Are the 74HCT245’s direction configured the right way around regarding RWB? Do the I/O devices even work correctly with those buffers, arranged that way?
I think I have all needed signals on the expansion port, and also added several VCC and GND lines to it. Did I miss some?
Did I cover all the CPU’s “mystery” pins correctly?