Bus timing for 65c816 is potentially more challenging than timing for 65c02. Although address lines A15-A0 have the same job as on a 6502, D7-D0 carry extra activity. As noted in the data sheet, "The Data/Bank Address Bus pins provide both the Bank Address and Data. The bank address is present during the first half of a memory cycle, and the data value is read or written during the second half of the memory cycle." I started this thread because I thought it was worth discussing the details.

First, two diagrams. Below is my own edited version of Figure 4-1 from the '816 Data Sheet (Sept 2010 version). To put all the various delays in perspective I squeezed and stretched things so that the diagram is now approximately to scale along the horizontal axis.

Assuming a 70 ns cycle (14 MHz), WYSIWYG! WDC's original diagram has two errors of omission; my corrections are shown in blue (I added 2 missing arrowheads and the value name tBH). Proofreaders welcome. Also, from Table 4-2, I copied in the actual delays (in ns.) that pertain to 5V operation. The clock rise & fall times have not been adjusted to scale.
The next diagram (below) shows the extra activity on D7-D0, as compared to a 6502. D7-D0 are bidirectional, meaning that the CPU and the system board must both drive them -- but of course never simultaneously, which would amount to a collision (aka bus contention).
It's when the bus reverses direction that there's potential for a problem. A graceful reversal demands that the CPU release the bus before the memory or transceiver on the system board commences to drive it. Likewise the system board must release the bus before the CPU commences to drive it.

With 6502, it's easy. The bus never reverses direction except when read cycles are interspersed with writes. More to the point, neither the processor nor the system board (if it's properly designed) drives the data bus during Phase 2 low.

The "dead time" during 65c02 Phase 2 low is actually extremely valuable! It acts as a timing cushion that accommodates real-world variability -- for example, the tri-state enable & disable delays of the memory or transceiver that drives the bus, the delay of the glue logic in control of that, and the timing variability of the CPU's own internal bus driver. These delays can't be exactly predicted, and vary independently of one another. The dead time will be at its most brief when the device releasing is at its slowest and the device asserting is at its fastest. But the 6502 has plenty of wiggle room. The dead time is nominally 50% of the cycle, and won't get eaten up even after a margin is subtracted for variability in logic and tri-state delays.

With the '816, it's a stickier situation. Even in the case of successive read cyles, the bus must reverse direction. But really the crucial issue is...

• in Phase 2 low the CPU drives the Bank Address onto the data bus
• instantly thereafter, during Phase 2 high, memory drives data on the bus
• instantly thereafter it's back to the CPU driving the Bank Address onto the data bus

Stated another way, the dead time is zero even before a margin is subtracted for variability in logic and tri-state delays. Of course the variability might trend in your favor, creating a dead time. But it equally might trend the other way and create bus contention. I'm not aware of any really good solution for this.

What I'd like to determine is how best to design for the '816. Here's Figure 5-1.I'm sure this circuit has been used successfully many times, but it's somewhat vague. Is it safe to assume that, for the "74x245" bus transceiver, we can use anything from a 74LS245 to a 74BCT245? What if it's a CPLD or some other device that connects to D7-D0? How do we ensure that the bus enable and bus inhibit times are appropriate for avoiding bus collisions with the '816? Here's what we have to go on:

• I think we can accept tBAS (max 33ns) as the maximum delay from Phase 2 low until the '816 asserts the bus. What's the minimum?
  
• Likewise, tBH (min 10) can be interpreted as the minimum delay from Phase 2 high until the '816 releases the bus. What's the maximum?
  
• tDHR (min 10) can be interpreted as the minimum delay from Phase 2 low until the system board releases the bus. What's the maximum?
  
• As for the delay from Phase 2 high until the system board asserts the bus, none of the values in the diagram seems directly pertinent, either for maximum or minimum.

Is there something I've overlooked, or do these specifications fail to tell the whole story?

cheers,
Jeff

[Edits: 2 more missing specs noted in the last paragraph. Altered text and new "data bus activity" and to clarify contention issue.]

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

That's on my list of "someday" projects, too. <sigh> Yes, including the duty cycle on Phi2.
This is by no means just an '816 issue; there are other examples, including 8085, 8088 and 8086. I recall a case where a friend's employer had an 8086 design. It became obligatory to include bus transceivers to connect the EPROMs to the data bus, not because of insufficient drive current but because the EPROMs were too slow letting go of the bus.

Even in light of this, my speculation is that modern RAMs could be connected directly to the '816's D7-D0 -- ie, without a transceiver. But there would be benefits from including the transceiver anyway, such as relieving some of the capacitive loading seen by the CPU.

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

You have spent much more time studying this than I did Jeff - nice work!

On my SBC-3 & 4, I used a CPLD to manage the latching of the bank address. This was a simple latch, equivalent to the 74573. It was transparent during PHI2 low, and latched when PHI2 was high. I didn't bother with any delays or shifting of PHI2. This worked flawlessly up to and beyond 14MHz as long as my bus loading was light. With more devices on the bus, lower speeds (8-12MHZ) worked well. My CPLD's were typically 15ns Xilinx 95108's.

As far as managing the databus, the tri-state buffers used in the CPLD also used PHI2 & R/W in addition to the address decoding logic to select the CPU, Memory, or IO as needed. No special attention to the PHI2 edges were needed.

SBC-3 went one step further in using the PHI2 low period to perform video data transfer.

I cannot say it did not cause bus contention, but I can say it didn't affect the operation of my two systems.

Just my two cents.

Daryl

_________________
Please visit my website -> https://sbc.rictor.org/

In a different thread,Hi, Ed. Slippery subjects! Bear with me please.

Although a 6502 (or 'C02) performs no transfer on the data bus while phi2 is low, that's not the same as saying the phi2 low period has no function. Of course the CPU has internal operations it performs, but also the period of external inactivity affords a valuable timing margin for the changeover when one device relinquishes the bus (possibly in a laggardly fashion) and another device takes over (possibly very promptly). To try to execute these actions simultaneously would be dubiously advisable, but with the '02 we're safe because the bus is relinquished at the end of one phi2 and not taken over until the beginning of the one following. The '816 is less forgiving, hardware-wise, because it does command those actions to occur simultaneously. The 2nd diagram in the lead post illustrates this comparison.

In a case where an '816 has been dropped into an '02 design (Garth's workbench computer is an example of this), the bank address will appear on the data bus during phi2 low -- even though the bank address may be zero, and there's no address latch to capture those bits anyway! So, there's no transfer that occurs, but the valuable period of inactivity -- the dead zone -- has been lost. By all indications I've seen so far, this is virtually guaranteed to result in some degree of bus contention, albeit transient (lasting perhaps 10% or less of one cycle). The duration will depend on how much mismatch exists between the enable/inhibit times of the CPU's data bus drivers and the enable/inhibit times of the main board device(s) -- the transceiver, if used; otherwise the enable/inhibit times of each memory and peripheral device.

BTW bus contention, though definitely undesirable, is not necessarily a show-stopper, and in some cases may be tolerated by the system and go unnoticed. Probably the effects will be mitigated by good PCB layout and proper supply bypassing -- as well as wimpy drive capability in the peripheral device!

The video access you refer to uses the same time slice (ie, phi2 low) but it uses a different bus. IOW the RAM data bus does not connect directly to the CPU data bus. There's a transceiver there, and double accesses on the RAM side are not reflected on the CPU side. The '02 vs '816 question (re what happens in the phi2 low time) remains a separate matter. The BBC Model B uses a 74LS245 to connect (and to isolate) the two buses. I haven't checked other BBC models or the Apple ][ but I expect they have something similar.

cheers,
Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Thanks for speaking up, Daryl. And nice job on the SBC's!

As for video data transfer, the double accesses have no bearing on the contention issue since, as noted above in regard to the Beeb, a separate bus is used.

cheers,
Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thanks, Garth -- I'm glad you mentioned the '802. According to Wikipedia,
The pertinent point (to me) is that WDC and GTE did not consider the 65816 as being a drop-in replacement for the 6502. Yes there are minor differences in pin-out but I suspect another factor was their concern about bus contention issues during the phi2 low time which might pose a problem with pre-existing hardware. The '802 eliminated the issue by eschewing multiplexing and instead sticking with the 6502 policy of a "dead zone" on the data bus during phi2 low.

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

Hi, BDD. Glad to hear someone's put that diagram to use! I know that, as a rule, timing diagrams aren't done to scale, but in this case I got frustrated and made an exception, using the assumption of 14 MHz.

The right track, eh? I know you're an avid railroad fan -- and it looks as if your interest in trains is influencing your vocabulary! But let's see if I follow what you're saying. Maybe you're not on the right track. Timing values do not stay constant as a percentage of machine cycle time.

An example would be helpful. tADS (the delay from phi2 low until A15-A0 are valid) is listed as max 30 ns. At 14Mhz this is about 43% of the 70 ns cycle time. If we choose a 140 ns cycle time (7 MHz), tADS is still max 30 ns -- now about 21% of the cycle time. If we shorten the cycle time, same thing -- still max 30 ns, but the percentage has changed again.

So, my diagram is only to scale for the case of 14 Mhz (a 70 ns cycle). If the cycle time is altered you'd need a new diagram if you want to remain in scale -- which is probably why scaled timing diagrams are uncommon; you need a new diagram for every operating frequency.

cheers,
Jeff

ps- thanks for the remarks on ABT series devices -- are they preferable to BCT? Among the 5V-capable families, what's best? There are so many families now it's getting like alphabet soup! This could merit a new thread -- it's not just an '816 issue.

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

(Jeff, thanks for the comment on my comment. I think I intended to prove something by mentioning systems which do double-duty in each clock cycle: perhaps prove that all the address decoding and setup times can be met within a half-cycle. But it doesn't quite prove that, and it doesn't completely address the problem even if it did - sorry about that. I think I'd be happy with the possibility of brief contention, or happy that it's soluble without throwing half a cycle of dead time at it, but what's not happy is that a 6502 leaves the databus floating during phi1, whereas the 816 drives it. There might be system designs where peripherals also drive the bus during phi1, and that would then be a contention problem. Hence the isolating tristate in WDC's sketch. On a separate note, I wonder if the '802 drives the bus during phi1 - I'd bet that it is the same die, with a different bond-out.)

Edit: I lose the bet - see Arlet's later post

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

I can see that guaranteed compatibility might well prove the point that the data bus must be undriven during phi1, but I wouldn't follow the other conclusion: it's easy enough to put extra pads on a chip and bond-out different subsets of them to the pins to make different products. And it's terribly difficult to design a chip, so even two related designs (like 6501 and 6502) is a more costly project than to make a single die with two bond options.

Having said, this die shot has 40 bond wires and no obvious sign of spare pads, which counts against my hypothesis!
viewtopic.php?p=15729#p15729

Cheers
Ed

It's quite plausible to say the published figures are conservative, but to say that in reality the actual delays scale proportionally with clock speed is a provocative statement -- I got derailed on that one! What else did you test besides tBH? Is this diagram a reasonable representation of what you used? (I like simple tests.)

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html