Nice to see the progress, Marco! And I like the photos of the piggybacked RAM chips.

Not so enthusiastic about your timing calculations, though. I guess you know it's simplistic (and falsely optimistic) to expect a system to run at a clock rate that's the reciprocal of memory cycle time. This allows zero ns for the CPU's end of the transaction.

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Thanks Jeff!

Yes indeed I know, however what I don’t know is:

Why is it running at 8 MHz? The EEPROM has better specs then specified? Will it fail over time?
What would be a safe clock speed if you know the specs of the slowest component?
What would be a safe clock speed if you don’t know the specs of the slowest component?

_________________
Marco

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

(There's another effect of binning: if 10% of the parts pass the test and go into the fastest bin, but the market only needs 5%, then some of the known fast parts can be marked as some slower grade and sold as such.)

Two other effects allow overclocking: the supply voltage and the temperature may not be worst case, and probably are not.

Another effect is that a critical path may pass through several components, any of which might have some margin beyond the spec. A fast gate in the glue logic might make up for an on-spec CPU and ROM.

So first of all the sum of all the propagation delays dictate the maximum frequency. Then it’s a bit of luck how much you can get above the specified frequency of the individual components.

Nevertheless I have different can- and crystal oscillators to determine the maximum frequency my computer will run on. However this could and will probably change every time I add a peripheral / PCB to my computer.





Indeed, I think that’s what Intel does with their CPU’s, normal versus “K” versions etc.


Of course I remember overclocking my ASUS motherboards, CPU, RAM and video cards back in the 90’s, and I had to provide sufficient cooling and raise the supply voltage of some components. Now I’m not doing that anymore, the PC’s nowadays are fast enough.

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Marco

The other thing to note is that a hobbyist has a different situation than a mass market manufacturer. If you need to ship a million computers and deal with the expense and negative press from getting a thousand returned as faulty, better to design with a safety margin. Likewise if you make medical equipment, better make it reliable. But if you're making one computer, and you'd be happy if it runs for an hour, that's a different situation.

(Several here, including Garth and Jeff, engineer things for a living, so they do need a safety margin as they have a reputation and a livelihood to protect.)

Better specs than specified? Okay, I think you're having some fun with the wording. But yes, sometimes a part has better performance than specified, as Garth explained. Here's the deal:
- If you stay within the specs then your design is guaranteed to work (timing-wise, I mean).
- If you violate the specs it doesn't mean your design is guaranteed to fail (but it might).

You need the specs for all components. That's because every clock cycle involves a transaction between the CPU and memory -- and the transaction happens sequentially, step by step. That means there's got to be enough time in the clock cycle for the total time taken by all the steps.

A read cycle goes like this:

• (cpu): takes some time to place an address on the address bus
• (mem): takes some time to input that address, fetch the data stored there and put the data on the data bus
• (cpu): takes some time to input the data

A write cycle goes like this:

• (cpu): takes some time to place an address on the address bus and data on the data bus
• (mem): takes some time to input the address and data and perform the write

edit: oops! -- somehow I overlooked the last few posts until now! But it's just as you say. "the sum of all the propagation delays dictate the maximum frequency."

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

I did! +1

Of course, that makes sense.

Oops , now I see what I wrote…


Continuing my build:

After the EEPROM board, I build two new ones, the DUART and CLOCK / RESET boards. Since there was a lot of room left on the CLOCK / RESET board, I added the F18A video FPGA board to it.

DUART:


CLOCK, RESET & F18A:

Does it run CRYSIS?
No, but it lives!!!



The F18A isn’t decoded yet in the CPLD, but it starts up correctly and responds to the system reset.


Now I have to tidy up and complete the VHDL code, create a way to easily update my firmware onto MARC-3 S and adapt some software (monitor / ehbasic etc.).

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Marco