Does the 6502 have a lowest frequency? for example, 10HZ

The old NMOS 6502 could start to lose the data from its registers below 100kHz, but the CMOS ones can be stopped indefinitely with the clock high. WDC's current production can be stopped with the clock in either phase and won't lose info.

There is no minimum clock frequency for a CMOS processor (65C02 etc), but the clock must have the correct duty cycle. The low portion of the clock cycle can be no longer than 5 microseconds, while the high portion of the clock cycle can be of any length.

To run a 65C02 at a low speed, you need to hold the clock input high most of the time and pulse it briefly low at a suitable rate.

Again, WDC's 65c02's being made today can be high or low as long as you want. All the others (which are no longer made, like Rockwell, Synertek, GTE (CMD), etc.) must be kept low no more than 5µs at a time.

Much, much more important is the slew rate of the clock. When WDC says that their clocks have a maximum rise or fall time of 5ns, they mean it.

Very true, but generating a clock with a fast slew rate is easy. Run your oscilator at twice the desired frequency and divide it down using a 74AC74 connected to the 65C02 clock input with a short lead. This will give sub-nanosecond rise and fall times.

Nope. Look closely again at the 74AC timings; you'll see its rise and fall times are just a hair outside of WDC's specs.

You need to use those clock oscillator cans. That's the only thing that will work that's super cheap.

Also, 74F-series logic will also switch fast enough too, but just barely.

(I know this because I've done it. Look around the forum for my Kestrel-related problems. )

Hummm, yes, I see what you mean.

Using the 65C816 chip, where phi2 is an input and the clock oscilator also drives the main phi2 line through the rest of the machine puts a heavy capacitive load on the oscilator, requiring a powerful driver and, ideally, line termination to prevent reflections. I'm surprised the little oscilator cans can manage it.

I was thinking of the 65C02, where the clock oscilator ONLY drives the phi0 input on the CPU itself. In this case, the capacitive loading on the clock chip is low, and the 74AC series easily achieves the rise-time specifications required.

Quite possibly. In my next-generation Kestrel design, I'm going to drive the CPU clock from a can, plus one NAND gate as a buffer, feeding whatever other logic needs it. That keeps the CPU's clock nice and clean. I still have a few 74F00 gates left over from my last experiments with the Kestrel 1p3.

That will work. If you've got the spare gates, buffer the oscillator twice, with one buffer just feeding the CPU and the other feeding the rest of the system. This avoids propogation delay differences.