Multiple IRQ's with a video processor

[cbmeeks]

I've read the primer on IRQ's and I guess I'm just not getting it. If I have a SBC that has two VIA's and a video processor that supports an interrupt on each vertical blank, how does the CPU know which component triggered the interrupt? And, how would I tell the CPU that the video interrupt would always have priority?

Thanks

[DerTrueForce]

You read the Status Registers or Interrupt Flag Registers. There should be at least a bit in a register in an IRQ-enabled device that says "I've interrupted." A bit like a raised hand in a classroom.

You'd set the priority by the order in which you read the registers and clear the interrupts.

[GARTHWILSON]

That was one of the first articles I ever wrote, and I know my writing has improved since then. There's too much to do to take the time to re-write it though. Anyway, to expand on DerTrueForce's answer, see the half-dozen paragraphs or so starting two paragraphs above this short piece of example code:

Code: Select all

ISR: BIT  VIA1_STATUS    ; Check 6522 VIA1's status register without loading.
     BMI  SERVICE_VIA1   ; If it caused the interrupt, branch to service it.
     BIT  VIA2_STATUS    ; Otherwise, check VIA2's status register.
     BMI  SERVICE_VIA2   ; If that one did the interrupt, branch to service it.
     JMP  SERVICE_ACIA   ; If both VIAs say "not me," it had to be the 6551 ACIA.
 ;-------------          ; (Don't forget that the last ISR instruction to be
                         ;    executed must be RTI, not RTS.)

and also the area around this diagram:


If you want the video interrupt to be of such high priority that it can cut in on the servicing of other interrupts before those other ones' ISRs get a chance to turn off such interrupts and re-enable interrupting, you can put the video on the NMI input. We're often told to reserve the NMI for something drastic like power going down; but in most systems the people on 6502.org are making, what happens in the last milliseconds before power is gone is of no concern. If you have a system that remembers things when it's off, it probably has batteries and can turn itself off in an orderly fashion. Otherwise, if you accidentally pull the power cord, there's no time to store anything useful on a disc anyway.

[cbmeeks]

Ah, OK. I think I get it.

So for each VIA, for example, I would check the IFR ($0D) and if bit 7 is true (using BIT) then that VIA triggered an interrupt. Then, I would just simply check the VIA's in order of importance.

Now since my graphics processor doesn't really have a status register (Propeller), I could either make one or just use the NMI since I want it to be top priority always.

Thanks

[BigDumbDinosaur]

cbmeeks wrote:

So for each VIA, for example, I would check the IFR ($0D) and if bit 7 is true (using BIT) then that VIA triggered an interrupt. Then, I would just simply check the VIA's in order of importance.

It depends on how you are using the VIA. If only one interrupt has been enabled a "blind" BIT instruction to test for a VIA interrupt is sufficient. If two or more interrupts are enabled you'd have to load the IFR into the accumulator and start testing bits to determine what interrupted (with one exception if only two interrupts are enabled). With the 65C02 or 65C816 you can use BIT # to nondestructively test individual bits after loading the IFR into .A, and act accordingly.

[Klaus2m5]

And keep in mind, that interrupt handling really needs to be short. In a worst case scenario the video interrupt would occur just after a VIA interrupt. So even with having polled the video interrupt flags first you must be sure to still have enough time to service the video interrupt after any of the VIAs got serviced.

[GARTHWILSON]

If you put the video interrupt on NMI, it can cut in on the servicing of other interrupts; so in that case it doesn't matter if the other ISRs are short or not.

[Klaus2m5]

True, but NMI has the disadvantage that it cannot be temporarily suspended by SEI or after a reset.

[GARTHWILSON]

Hopefully the video chip has a reset input also, and it won't produce any interrupts until it is again set up to do so.

For suspending interrupts, instead of SEI, you can tell the IC not to interrupt until further notice, or mask NMIs in hardware with a separate gate, maybe a NAND gate. [Edited to fix "an AND" to say "a NAND".]

[PaulF]

GARTHWILSON wrote:

For suspending interrupts, instead of SEI, you can tell the IC not to interrupt until further notice, or mask NMIs in hardware with a separate gate, maybe an AND gate.

To DISABLE interrupts, you would need an OR gate or a NAND gate, as you want to hold the output high when interrupts are disabled. An AND can only force the output low. While this would disable NMI, since NMI is edge-triggered and not level-triggered, it would also cause an NMI as you disabled it!

[GARTHWILSON]

You're right! That's what I get for writing too late at night. I'll fix it.