Welcome, Valerio
This is a nice selection of improvements. For example the exchange instructions appeal to me -- something so simple, but so worthwhile. It's almost like having new address modes. For example, if you want (ind),X mode then just use XYZ -- ie; exchange X with Y -- and follow up by using (ind),Y mode.
Maybe you can tell us more about that I/O coprocessor, please.
-- Jeff
Code:
; new V6502 opcodes macros
phr: .macro ;AXY->SP: push A,X,Y to stack (useful for fast context switch)
.byte $8b
.endm
plr: .macro ;SP->YXA: pull A,X,Y from stack (useful for fast context switch)
.byte $ab
.endm
taz: .macro ;A->Z: copy A to zero page register (MSB base address)
.byte $1b
.endm
tza: .macro ;Z->A: copy zero page register to A
.byte $3b
.endm
txy: .macro ;X->Y: copy X to Y
.byte $9b
.endm
tyx: .macro ;Y->X: copy Y to X
.byte $bb
.endm
xyx: .macro ;X<->Y: exchange X with Y
.byte $eb
.endm
xax: .macro ;A<->X: exchange A with X
.byte $0b
.endm
xay: .macro ;A<->Y: exchange A with Y
.byte $2b
.endm
isp: .macro ;X -> S (lsb); A -> S msb: copy X and A to S (16 bit stack pointer)
.byte $4b
.endm
tsp: .macro ;S lsb -> X; S msb -> A: copy S to X and A
.byte $5b
.endm
jsrx: .macro arg1 ;JSR ($XXXX,X) jump vector table indexed by X
.byte $fc
.word arg1
.endm
_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html
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