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PostPosted: Mon Nov 20, 2017 12:11 pm 
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Part (6) of the Adventure is now posted on Stardot:
http://stardot.org.uk/forums/viewtopic. ... 57#p182757


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PostPosted: Mon Nov 20, 2017 12:33 pm 
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Excellent - so a logic analyser in this case needs only a £15 capture board, and just ten signal lines: the data bus, the clock, and RnW. By sufficient cleverness, you've removed the need for Sync, and so in the case of the Beeb the highly accessible Tube connector is adequate. Other machines will likely have expansion connectors with the right signals too.

(I'm going to borrow your photo, because photos are good:
Image
)

I'm going to guess that Reset is handy but not essential - handy for triggering - and also that stretched clocks or RDY-stalls might still cause the decoder some desynchronisation??


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PostPosted: Mon Nov 20, 2017 12:57 pm 
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BigEd wrote:
I'm going to guess that Reset is handy but not essential - handy for triggering - and also that stretched clocks or RDY-stalls might still cause the decoder some desynchronisation??

Concerning RDY:

On the Master 128, ignoring RDY is problematic, at least currently.

On the Model B, RDY is rarely (if ever) used, and clock stretching (which is used instead) doesn't cause a problem.

Concerning RST:

Reset is indeed handy for triggering, and for acquiring immediate lock on the instruction stream.

The Master has a GTE G65SC12 processor, which is one of the few to actually do three writes to the stack on reset. So if reset is omitted, this is actually seen as an interrupt, which works out fine and you get a correct initial value for PC.

The Model B has a Signetics SY6502A, and without reset you tend to see a long stream of BRK instructions, and the initial alignment is somewhat random:
Code:
0000 : 00 00    : BRK #00       A=00 X=?? Y=?? SP=?? N=0 V=0 D=0 I=1 Z=0 C=0 prediction failed
0000 : 00 00    : BRK #00       A=00 X=?? Y=?? SP=?? N=0 V=0 D=0 I=1 Z=0 C=0 prediction failed
0000 : 00 00    : BRK #00       A=00 X=?? Y=?? SP=?? N=0 V=0 D=0 I=1 Z=0 C=0 prediction failed
0000 : 00 00    : BRK #00       A=00 X=?? Y=?? SP=?? N=0 V=0 D=0 I=1 Z=0 C=0 prediction failed
0000 : 00 00    : BRK #00       A=00 X=?? Y=?? SP=?? N=0 V=0 D=0 I=1 Z=0 C=0 prediction failed
0000 : 00 00    : BRK #00       A=00 X=?? Y=?? SP=?? N=0 V=0 D=0 I=1 Z=0 C=0 prediction failed
0000 : 00 00    : BRK #00       A=00 X=?? Y=?? SP=?? N=0 V=0 D=0 I=1 Z=0 C=0 prediction failed
0000 : 00 00    : BRK #00       A=00 X=?? Y=?? SP=?? N=0 V=0 D=0 I=1 Z=0 C=0 prediction failed
0000 : 00 00    : BRK #00       A=00 X=?? Y=?? SP=?? N=0 V=0 D=0 I=1 Z=0 C=0 prediction failed
0000 : 00 00    : BRK #00       A=00 X=?? Y=?? SP=?? N=0 V=0 D=0 I=1 Z=0 C=0 prediction failed
0000 : 00 00    : BRK #00       A=00 X=?? Y=?? SP=?? N=0 V=0 D=0 I=1 Z=0 C=0 prediction failed
0000 : 00 FF    : BRK #FF       A=00 X=?? Y=?? SP=?? N=0 V=0 D=0 I=1 Z=0 C=0 prediction failed
A9D9 : 40       : RTI           A=00 X=?? Y=?? SP=?? N=0 V=0 D=0 I=0 Z=0 C=0
780D : D8       : CLD           A=00 X=?? Y=?? SP=?? N=0 V=0 D=0 I=0 Z=0 C=0
780E : A2 A2    : LDX #A2       A=00 X=A2 Y=?? SP=?? N=1 V=0 D=0 I=0 Z=0 C=0
7810 : FF       : ???           A=00 X=A2 Y=?? SP=?? N=1 V=0 D=0 I=0 Z=0 C=0
7812 : 9A       : TXS           A=00 X=A2 Y=?? SP=A2 N=1 V=0 D=0 I=0 Z=0 C=0
7813 : AD 4E FE : LDA FE4E      A=80 X=A2 Y=?? SP=A2 N=1 V=0 D=0 I=0 Z=0 C=0
7816 : 0A       : ASL A         A=00 X=A2 Y=?? SP=A2 N=0 V=0 D=0 I=0 Z=1 C=1
7817 : 48       : PHA           A=00 X=A2 Y=?? SP=A1 N=0 V=0 D=0 I=0 Z=1 C=1
7818 : F0 09    : BEQ 7823      A=00 X=A2 Y=?? SP=A1 N=0 V=0 D=0 I=0 Z=1 C=1
7823 : A2 04    : LDX #04       A=00 X=04 Y=?? SP=A1 N=0 V=0 D=0 I=0 Z=0 C=1
7825 : 86 01    : STX 01        A=00 X=04 Y=?? SP=A1 N=0 V=0 D=0 I=0 Z=0 C=1
7827 : 85 00    : STA 00        A=00 X=04 Y=?? SP=A1 N=0 V=0 D=0 I=0 Z=0 C=1

Dave


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PostPosted: Mon Nov 20, 2017 1:09 pm 
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Thanks Dave - of course I'd overlooked the trivial observation that if you can see the clock, you're not too worried about clock-stretching!


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PostPosted: Mon Nov 20, 2017 1:20 pm 
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Just a thought on RDY, at least in the case of Acorn's Master: it only kicks in for the vital reads and writes of I/O devices. It might be possible to get at least partial handling of these.

If they are loads and stores, not RMW, they will stretch the final access of the instruction, to two or even three cycles. If it's a store, I think that might give it a unique signature - I think it's even distinct from an interrupt, whose writes are in cycles 2,3,4. If it's a load, that's rather harder to spot. Having A0 visible would help here, half the time anyway. The more address bits the better the chance of seeing a difference between a stretched read and the next instruction fetch.

As noted elsewhere, if the decoder has some knowledge of which addresses will cause cycle-stretching, in the case that it has managed to model enough CPU state, it can predict which instructions will be affected. Even more specifically, if need be, the decoder could model which PC values hold instructions which stretch cycles. (I'm thinking of a configuration file, suitable for a given machine in the first case, and suitable for a given revision of software in the second case, containing suitable annotated lists of addresses, or address ranges.)

But coping with both the single wait state and the double wait state, without knowing which it will be, is perhaps more of a challenge.


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PostPosted: Mon Nov 20, 2017 1:41 pm 
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This is the mix of I/O accesses during the Master's first 1 second of life:
Code:
     75 AND
     70 BIT
    301 LDA
     20 LDX
     64 LDY
   1159 STA
    376 STX
    251 STY
    130 STZ
     52 TRB
     86 TSB

Or in a bit more detail:
Code:
     71 AND FE4E   
      2 AND FEE0   
     31 BIT FE18   
     39 BIT FE4D   
    102 LDA FE08   
     28 LDA FE19   
     28 LDA FE1A   
     65 LDA FE34   
     71 LDA FE4D   
      1 LDA FE4E   
      2 LDA FEE0   
     20 LDX FE4F   
     64 LDY FE4F   
     57 STA FE01   
     33 STA FE08   
      3 STA FE10   
     29 STA FE18   
      1 STA FE20   
    174 STA FE30   
      1 STA FE34   
    598 STA FE40   
      1 STA FE42   
     83 STA FE43   
      1 STA FE45   
      1 STA FE46   
      1 STA FE47   
      1 STA FE4B   
    111 STA FE4D   
      2 STA FE4D,X 
      2 STA FE4E   
     54 STA FE4F   
      1 STA FE6C   
      2 STA FE6D,X 
      1 STA FE8E   
     45 STX FE01   
    199 STX FE30   
      1 STX FE4C   
      1 STX FE4E   
    125 STX FE4F   
      1 STX FE63   
      4 STX FEE0   
    102 STY FE00   
     62 STY FE30   
     50 STY FE40   
     35 STY FE43   
      2 STY FE4F   
    130 STZ FE43   
     52 TRB FE34   
     86 TSB FE34

TRB/TSB are read-modify-write, and are used for the ACCON register (&FE34)

Almost all are absolute, but there are a couple of indexed stores:
Code:
81A7 : 9D 4D FE : STA FE4D,X    A=7F X=01 Y=80 SP=FF N=0 V=0 D=0 I=1 Z=0 C=0
81AA : 9D 6D FE : STA FE6D,X    A=7F X=01 Y=80 SP=FF N=0 V=0 D=0 I=1 Z=0 C=0
81A7 : 9D 4D FE : STA FE4D,X    A=7F X=00 Y=80 SP=FF N=0 V=0 D=0 I=1 Z=1 C=0
81AA : 9D 6D FE : STA FE6D,X    A=7F X=00 Y=80 SP=FF N=0 V=0 D=0 I=1 Z=1 C=0

This starts to get highly machine specific. In the case of the Master, to predict whether the IO cycle is extended by one or two wait states, you would need to try to predict the phase of the 1MHz clock. Using some of the address bits might help, but there will always be pathological cases.

At the moment, the instruction table includes just the minimum number of cycles for each instruction. I was wondering whether to extend this to somehow encode the expected set of bus cycles. That would allow every write to be validated, and would give an early indication that things are out of sync.

Dave


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PostPosted: Mon Nov 20, 2017 1:48 pm 
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Ah, I hadn't thought of TRB/TSB! Interesting data, for sure.

(From my perspective, this is already a great piece of work, and it's a question of whether it can be pushed a little further, without the expectation that it will be watertight for all cases. If Sync is visible, it's watertight, and if RDY is not in play, or is visible, it's watertight. That's a great starting point!)

So, I wouldn't go anywhere near trying to model the phase of the two clocks which the Master switches between... The idea of knowing the possible and the likely timing behaviour of instructions though, that might well help.


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PostPosted: Mon Nov 20, 2017 3:03 pm 
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Here's a concrete example of how it goes wrong on the Master without RDY connected.

With RDY connected, you get:
Code:
???? :          : RESET !!      A=?? X=?? Y=?? SP=?? N=? V=? D=0 I=1 Z=? C=?
E364 : A9 40    : LDA #40       A=40 X=?? Y=?? SP=?? N=0 V=? D=0 I=1 Z=0 C=?
E366 : 8D 00 0D : STA 0D00      A=40 X=?? Y=?? SP=?? N=0 V=? D=0 I=1 Z=0 C=?
E369 : 78       : SEI           A=40 X=?? Y=?? SP=?? N=0 V=? D=0 I=1 Z=0 C=?
E36A : A9 53    : LDA #53       A=53 X=?? Y=?? SP=?? N=0 V=? D=0 I=1 Z=0 C=?
E36C : 8D 8E FE : STA FE8E      A=53 X=?? Y=?? SP=?? N=0 V=? D=0 I=1 Z=0 C=?
E36F : 20 90 E5 : JSR E590      A=53 X=?? Y=?? SP=?? N=0 V=? D=0 I=1 Z=0 C=?
E590 : A9 0F    : LDA #0F       A=0F X=?? Y=?? SP=?? N=0 V=? D=0 I=1 Z=0 C=?
E592 : 85 F4    : STA F4        A=0F X=?? Y=?? SP=?? N=0 V=? D=0 I=1 Z=0 C=?
E594 : 8D 30 FE : STA FE30      A=0F X=?? Y=?? SP=?? N=0 V=? D=0 I=1 Z=0 C=?
E597 : 60       : RTS           A=0F X=?? Y=?? SP=?? N=0 V=? D=0 I=1 Z=0 C=?
E372 : 4C 20 80 : JMP 8020      A=0F X=?? Y=?? SP=?? N=0 V=? D=0 I=1 Z=0 C=?
8020 : A9 FE    : LDA #FE       A=FE X=?? Y=?? SP=?? N=1 V=? D=0 I=1 Z=0 C=?
8022 : 1C 34 FE : TRB FE34      A=FE X=?? Y=?? SP=?? N=1 V=? D=0 I=1 Z=0 C=?
8025 : 9C DD DF : STZ DFDD      A=FE X=?? Y=?? SP=?? N=1 V=? D=0 I=1 Z=0 C=?
8028 : 1C 66 03 : TRB 0366      A=FE X=?? Y=?? SP=?? N=1 V=? D=0 I=1 Z=0 C=?
802B : D8       : CLD           A=FE X=?? Y=?? SP=?? N=1 V=? D=0 I=1 Z=0 C=?
802C : A2 FF    : LDX #FF       A=FE X=FF Y=?? SP=?? N=1 V=? D=0 I=1 Z=0 C=?
802E : 9A       : TXS           A=FE X=FF Y=?? SP=FF N=1 V=? D=0 I=1 Z=0 C=?
802F : 8E 63 FE : STX FE63      A=FE X=FF Y=?? SP=FF N=1 V=? D=0 I=1 Z=0 C=?
8032 : A9 CF    : LDA #CF       A=CF X=FF Y=?? SP=FF N=1 V=? D=0 I=1 Z=0 C=?
8034 : 8D 42 FE : STA FE42      A=CF X=FF Y=?? SP=FF N=1 V=? D=0 I=1 Z=0 C=?
8037 : A0 20    : LDY #20       A=CF X=FF Y=20 SP=FF N=0 V=? D=0 I=1 Z=0 C=?
8039 : A2 0A    : LDX #0A       A=CF X=0A Y=20 SP=FF N=0 V=? D=0 I=1 Z=0 C=?
803B : 20 E4 98 : JSR 98E4      A=CF X=0A Y=20 SP=FD N=0 V=? D=0 I=1 Z=0 C=?
98E4 : 08       : PHP           A=CF X=0A Y=20 SP=FC N=0 V=0 D=0 I=1 Z=0 C=1
98E5 : 78       : SEI           A=CF X=0A Y=20 SP=FC N=0 V=0 D=0 I=1 Z=0 C=1
98E6 : 20 06 99 : JSR 9906      A=CF X=0A Y=20 SP=FA N=0 V=0 D=0 I=1 Z=0 C=1
9906 : A9 02    : LDA #02       A=02 X=0A Y=20 SP=FA N=0 V=0 D=0 I=1 Z=0 C=1
9908 : 8D 40 FE : STA FE40      A=02 X=0A Y=20 SP=FA N=0 V=0 D=0 I=1 Z=0 C=1
990B : A9 82    : LDA #82       A=82 X=0A Y=20 SP=FA N=1 V=0 D=0 I=1 Z=0 C=1
990D : 8D 40 FE : STA FE40      A=82 X=0A Y=20 SP=FA N=1 V=0 D=0 I=1 Z=0 C=1

With RDY unconnected you get:
Code:
???? :          : RESET !!      A=?? X=?? Y=?? SP=?? N=? V=? D=0 I=1 Z=? C=?
E364 : A9 40    : LDA #40       A=40 X=?? Y=?? SP=?? N=0 V=? D=0 I=1 Z=0 C=?
E366 : 8D 00 0D : STA 0D00      A=40 X=?? Y=?? SP=?? N=0 V=? D=0 I=1 Z=0 C=?
E369 : 78       : SEI           A=40 X=?? Y=?? SP=?? N=0 V=? D=0 I=1 Z=0 C=?
E36A : A9 53    : LDA #53       A=53 X=?? Y=?? SP=?? N=0 V=? D=0 I=1 Z=0 C=?
pc: prediction failed at 5353 old pc was E36C
5353 :          : INTERRUPT !!  A=53 X=?? Y=?? SP=?? N=0 V=1 D=0 I=1 Z=1 C=1 prediction failed
9020 : FF E3 71 : BBS7 E3,9093  A=53 X=?? Y=?? SP=?? N=0 V=1 D=0 I=1 Z=1 C=1
9093 : 0F 85 F4 : BBR0 85,9089  A=53 X=?? Y=?? SP=?? N=0 V=1 D=0 I=1 Z=1 C=1
9089 : 30 FE    : BMI 9089      A=53 X=?? Y=?? SP=?? N=0 V=1 D=0 I=1 Z=1 C=1
908B : 0F 60 DA : BBR0 60,9067  A=53 X=?? Y=?? SP=?? N=0 V=1 D=0 I=1 Z=1 C=1
9067 : E3       : NOP           A=53 X=?? Y=?? SP=?? N=0 V=1 D=0 I=1 Z=1 C=1
9068 : E5 4C    : SBC 4C        A=33 X=?? Y=?? SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
906A : 80 A9    : BRA 9015      A=33 X=?? Y=?? SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
9015 : 1C 34 FE : TRB FE34      A=33 X=?? Y=?? SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
9018 : 9C DD DF : STZ DFDD      A=33 X=?? Y=?? SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
901B : 1C 66 03 : TRB 0366      A=33 X=?? Y=?? SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
901E : D8       : CLD           A=33 X=?? Y=?? SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
901F : A2 FF    : LDX #FF       A=33 X=FF Y=?? SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
9021 : 9A       : TXS           A=33 X=FF Y=?? SP=FF N=1 V=0 D=0 I=1 Z=0 C=1
pc: prediction failed at FFFF old pc was 9022
FFFF :          : INTERRUPT !!  A=33 X=FF Y=?? SP=FC N=1 V=1 D=0 I=1 Z=1 C=1 prediction failed
pc: prediction failed at CFCF old pc was CFA9
CFCF :          : INTERRUPT !!  A=33 X=FF Y=?? SP=F9 N=1 V=1 D=0 I=1 Z=1 C=1 prediction failed
20A0 : A2 0A    : LDX #0A       A=33 X=0A Y=?? SP=F9 N=0 V=1 D=0 I=1 Z=0 C=1
pc: prediction failed at 803B old pc was 20A2
803B : 20 E4 98 : JSR 98E4      A=33 X=0A Y=?? SP=F7 N=0 V=1 D=0 I=1 Z=0 C=1
98E4 : 08       : PHP           A=33 X=0A Y=?? SP=F6 N=0 V=1 D=0 I=1 Z=0 C=1
98E5 : 78       : SEI           A=33 X=0A Y=?? SP=F6 N=0 V=1 D=0 I=1 Z=0 C=1
98E6 : 20 06 99 : JSR 9906      A=33 X=0A Y=?? SP=F4 N=0 V=1 D=0 I=1 Z=0 C=1
9906 : A9 02    : LDA #02       A=02 X=0A Y=?? SP=F4 N=0 V=1 D=0 I=1 Z=0 C=1
9908 : 8D 40 FE : STA FE40      A=02 X=0A Y=?? SP=F4 N=0 V=1 D=0 I=1 Z=0 C=1
990B : 02 A9    : NOP #A9       A=02 X=0A Y=?? SP=F4 N=0 V=1 D=0 I=1 Z=0 C=1
990D : 82 8D    : NOP #8D       A=02 X=0A Y=?? SP=F4 N=0 V=1 D=0 I=1 Z=0 C=1
pc: prediction failed at 8282 old pc was 990F
8282 :          : INTERRUPT !!  A=02 X=0A Y=?? SP=F1 N=1 V=0 D=0 I=1 Z=1 C=0 prediction failed
pc: prediction failed at FFFF old pc was FFA9
FFFF :          : INTERRUPT !!  A=02 X=0A Y=?? SP=EE N=1 V=1 D=0 I=1 Z=1 C=1 prediction failed
pc: prediction failed at 0A0A old pc was 4F8E
0A0A :          : INTERRUPT !!  A=02 X=0A Y=?? SP=EB N=0 V=0 D=0 I=1 Z=1 C=0 prediction failed

The biggest issue is that the wait-state extended writes look like three consecutive writes, which triggers the interrupt detection logic.

Interestingly, it regains sync in time for the TRB, and handles that fine. So I think accesses to &FE34 must be at 2MHz.

Now, if the interrupt detection logic looked specifically for writes in cycles 2, 3 and 4, then that might help. I have a vague recollection that sometimes the interrupt response is delayed (e.g. for a taken branch). So there may need to be some exceptions....

Dave


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PostPosted: Mon Nov 20, 2017 4:05 pm 
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hoglet wrote:
I have a vague recollection that sometimes the interrupt response is delayed (e.g. for a taken branch).

This thread talks about that. But better sources for the information may exist.

How easy or awkward would it be to add A0 to the signals you're capturing? A0 will clearly indicate interrupts if you know when the opcode fetch is.

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PostPosted: Mon Nov 20, 2017 4:26 pm 
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I see the hazard the 'C02 presents in having nearly any opcode be valid. I'm surprised it takes so long to resync.

But, a possible hope: the E3 NOP, that would normally pre-read the next instruction, and then the next instruction would follow. If that next instruction wasn't the same both times, then you know you're out of sync. So the NOP wasn't a fetch, which means the previous instruction was wrong. So it must have been either the 60 or the DA...


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PostPosted: Mon Nov 20, 2017 5:36 pm 
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Ed,

This is the best "simple" heuristic I can come up with for dealing with the wait states on IO access on the Master, when rdy is not available:
Code:
   // Ugly hack to try to remain in sync if rdy is not available
   if ((bus_cycle == cycle_count - 1) && (arguments.idx_rdy < 0) && (instr->len == 3)) {
      if ((op2 == 0xfc) ||                 // &FC00-&FCFF
          (op2 == 0xfd) ||                 // &FD00-&FDFF
          (op2 == 0xfe && (
             ((op1 & 0xE0) == 0x00) ||     // &FE00-&FE1F
             ((op1 & 0xC0) == 0x40) ||     // &FE40-&FE7F
             ((op1 & 0xE0) == 0x80) ||     // &FE80-&FE9F
             ((op1 & 0xE0) == 0xC0)        // &FEC0-&FEDF
             ))) {
         if (*(bus_data_q + 1) == bus_data) {
            cycle_count++;
         }
      }
   }

What this is doing is looking for the devices where wait states are known to be added, and then skips any repeated values at the end of the bus cycle.

That works well for writes:
Code:
0 8d 1 1
1 8e 1 1
2 fe 1 1
3 53 0 1
4 53 0 1
5 53 0 1
E36C : 8D 8E FE : STA FE8E      A=53 X=?? Y=?? SP=?? N=0 V=? D=0 I=1 Z=0 C=?
0 20 1 1
1 90 1 1
2 98 1 1
3 e3 0 1
4 71 0 1
5 e5 1 1
E36F : 20 90 E5 : JSR E590      A=53 X=?? Y=?? SP=?? N=0 V=? D=0 I=1 Z=0 C=?

But not for reads:
Code:
0 ad 1 1
1 4d 1 1
2 fe 1 1
3 40 1 1
E673 : AD 4D FE : LDA FE4D      A=40 X=09 Y=0E SP=0B N=0 V=0 D=0 I=1 Z=0 C=1
0 c0 1 1
1 10 1 1
E676 : C0 10    : CPY #10       A=40 X=09 Y=0E SP=0B N=1 V=0 D=0 I=1 Z=0 C=0
0 3c 1 1
1 2d 1 1
2 79 1 1
3 02 1 1
E678 : 3C 2D 79 : BIT 792D,X    A=40 X=09 Y=0E SP=0B N=0 V=0 D=0 I=1 Z=1 C=0

Which should be:
Code:
0 ad 1 1
1 4d 1 1
2 fe 1 1
3 40 1 1
4 c0 1 1
E673 : AD 4D FE : LDA FE4D      A=40 X=09 Y=0E SP=0B N=0 V=0 D=0 I=1 Z=0 C=1
0 10 1 1
1 3c 1 1
E675 : 10 3C    : BPL E6B3      A=C2 X=01 Y=00 SP=F1 N=1 V=0 D=0 I=1 Z=0 C=1
0 2d 1 1
1 79 1 1
2 02 1 1
3 ff 1 1
E677 : 2D 79 02 : AND 0279      A=C2 X=01 Y=00 SP=F1 N=1 V=0 D=0 I=1 Z=0 C=1

The problem is, in the read case that the value on the data bus will change.

So there really is no clue at all that wait states are present.

You know, I am thinking of trying to model the phase of the 1MHz clock!

For anyone else that's following along, the only reason I'm still digging in this hole is that for another Acorn related project we (specifically Dominic) have in mind, it would be very advantageous to be able to track the 6502's instruction stream without the use of Rdy. So I'm currently exploring this on a branch, and do not expect this to ever become mainstream. It's just too machine specific.

Dave


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PostPosted: Mon Nov 20, 2017 6:18 pm 
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Location: England
Well, that's not bad a bit of code, and is an improvement.

In the case that it went wrong, there are two questions: when can you first tell, and how far back would you need to rewind. As it's a Master, we know that accesses to page FE are a most likely cause of loss of synchronisation, so the finger points at the LDA which might have been stretched.

But indeed, in the case of a Master, the 1MHz clock is in exactly one of two states, and remains so, and so that means just one alternate hypothesis - two passes through the data perhaps - to see which one gives rise to fewest warnings or conflicts.

(One interesting thing about a possible loss of sync, is that if the sync has gone wrong, the machine model will start to go wrong. So for example a flag which controls a branch may be a fiction, and the fictitious branch may get the wrong cycle count. I'm not sure if that makes anything worse though.)


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PostPosted: Mon Nov 20, 2017 6:20 pm 
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Posts: 352
So, this seems to work:
Code:
   // Ugly hack to try to remain in sync if rdy is not available
   if ((bus_cycle == 3) && (arguments.idx_rdy < 0) && (instr->len == 3)) {
      if ((op2 == 0xfc) ||                 // &FC00-&FCFF
          (op2 == 0xfd) ||                 // &FD00-&FDFF
          (op2 == 0xfe && (
             ((op1 & 0xE0) == 0x00) ||     // &FE00-&FE1F
             ((op1 & 0xC0) == 0x40) ||     // &FE40-&FE7F
             ((op1 & 0xE0) == 0x80) ||     // &FE80-&FE9F
             ((op1 & 0xE0) == 0xC0)        // &FEC0-&FEDF
             ))) {
         if (opcode == 0x9D) {
            // STA abs, X which has an unfortunate dummy cycle
            cycle_count += 2 + mhz1_phase;
         } else {
            cycle_count += 1 + mhz1_phase;
         }
      }
   }
   // Toggle the phase every cycle
   mhz1_phase = 1 - mhz1_phase;

But it required the phase to be set correctly initially, as on the real hardware apparently it varies, i.e. sometimes the first store looks like:
Code:
0 8d 1 1
1 8e 1 1
2 fe 1 1
3 53 0 1
4 53 0 1
E36C : 8D 8E FE : STA FE8E      A=53 X=?? Y=?? SP=?? N=0 V=? D=0 I=1 Z=0 C=?

And other times it looks like:
Code:
0 8d 1 1
1 8e 1 1
2 fe 1 1
3 53 0 1
4 53 0 1
5 53 0 1
E36C : 8D 8E FE : STA FE8E      A=53 X=?? Y=?? SP=?? N=0 V=? D=0 I=1 Z=0 C=?

I guess we could possibly combine the two approaches.

What's encouraging is that if you do get the phase correct, the output is identical to the decoder when rdy is used.

Dave


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PostPosted: Sun Dec 03, 2017 6:06 pm 
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Posts: 352
Time for another update.

First, to close off the previous topic (SYNC-less and RDY-less decoding on the Master 128), it turns out this is actually possible. It involves predicting when the Master 128 would use RDY to insert wait states (based on the address accessed) and having the decoder do the same. This is behaviour enabled with a "--machine=master" command line flag. While not in any way generic, it proves this is possible if needed. The additional code is quite small.

Next, I worked on one of the loose ends: supporting Decimal Mode. This is now in place, and the decoder correctly track all the eight different variations of Bruce Clark's BCD tests (including all flags, and illegal inputs). This works on the 6502 and the 65C02, where the extra cycle needs to be accomadated.

After that, I've been trying to prove the SYNC-less decoder by running Klaus Dormann's 6502 and 65C02 functional tests. This found bugs in:
- TRB/TSB, where I was grabbing the operand from the wrong cycle
- BBR/BBS, where the sequence of bus cycles was not quite as expected (the fetch of the third byte of the instruction is somewhat delayed)
- plus a few other instructions which had incorrect cycle counts (transcription errors on my part).

Rather frustratingly, at least on my system, the FX2 driver for Sigrok seems to give up randomly after ~30s of capture. This prevents the capture of a complete run of Klaus's test suite (which takes just over a minute on the Master, and 2 minutes on the Electron). The reason, I think, is that asynchronous capture of 16 bits @ 12MHz is a significant load on both the USB bus, and on the system. There is also very little buffering on the FX2 device itself. If it were possible to capture synchronously, on the falling edge of Phi2, then the data rate (and file size) would be reduced 6x.

After reading around a bit more, I stumbled across the fx2pipe utility which purports to support synchronous captures from the FX2. A few changes are needed to allow this to compile on a modern Linux system (Ubuntu 16.04). Plus a change to capture on the falling edge, rather than the rising clock edge.

Using fx2pipe it's possible to capture indefinitely, and so I've been successful in verifying against the complete Dormann tests.

It's also possible (if slightly crazy) to use fx2pipe and decode6502 in a pipe that runs continuously:
Code:
fx2pipe -d=1d50:608d  -a 2>/dev/null | ./decode6502  -s -h -y --sync= --phi2= | egrep "FEE1|FEE3|FEE5|FEE7"

More details on some of the above can be found elsewhere.

Dave


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PostPosted: Thu May 31, 2018 10:26 am 
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Posts: 2
Dave,

Was very interested to read your posts on your mos6502 protocol decoder for sigrok.

I am looking to disassemble an old Tektronix 1220/1225/1230 series logic analyser that uses 6502 processors so was very interested in trying your 6502 disassembler under sigrok PulseView. However, the documentation on adding a new protocol decoder seems to be rather thin. There is quite a bit on writing one but nothing on how to install it.

I am interested in experimenting with your mos6502 disassembler Protocol Decoder and have tried copying your __init__.py, pd.py, and tables.py files from github into a new directory mos6502 under

C:/Program Files (x86)/sigrok/PulseView/share/libsigrokdecode/decoders

However, when I run PulseView it does not appear to have detected the new decoder and added it to the decoder menu.

I have also tried copying the contents of AC97 else where and putting the new code into the ac97 directory. PulseView seems to still use the old AC97 code if I try to select AC97.

How do I add an experimental protocol decoder to PulseView and have it visible in the decoder menu?

Do I have to rebuild the entire PulseView suite from sources every time?

Thanks for your help

Peter


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