This discussion on the retro computing stackexchange site might be of interest:

Mapping more than 64kb of address space
(How to make some kind of MMU without buying an expensive obsolete MMU chip)

(I see Garth's primer gets a mention and an endorsement!)

In fact the site generally might be of interest. It's a Q&A site, where the questions are supposed to be a single clearly stated question, and anyone can submit an answer. Both questions and answers can also have a comment stream, and in some kind of wiki fashion answers can also be edited. Questions, answers, and comments can be voted on, such that, one hopes, the best ones rise to the top.

Interesting how no one mentioned use of programmable logic to implement the MMU.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

They were talking about using actual period parts, so probably they simply don't think of it in the first place. (I suspect that many there may be "period purists.") As I understand it, you need a fairly large PLD for that job. I can think of a way to switch out a window of memory with an activation signal, a register(or two), and some AND gates, though.

What I would like to see would be a byte-wide 'ls670 in which the mapping side is Read-only and the other side is read/Write. Or, an 8x8 dual-port ram would be nice. The Cypress or IDT 1K or 2K would be overkill.

I suppose I could make a piggy-back stack of four or more http://www.alldatasheet.com/datasheet-pdf/pdf/127351/NSC/DM74ALS996.html, but the only place I see them in dip is ebay.

_________________
"I am endeavoring, ma'am, to create a mnemonic memory circuit... using stone knives and bearskins." -- Spock to Edith Keeler

Four 670's can accomplish this, as you probably realize. (It's the same arrangement as with my KK Computer -- see the block diagram ). One pair of 670's forms an 8-bit wide memory which accepts writes from the data bus and which reads to address-related logic. The other pair forms an 8-bit wide memory that accepts writes from the data bus and also reads back to the data bus. Btw the 74HC670 is still an active part, available in DIP and SMD.

Stacking up a bunch of 573's (or 574's) is another option, but you have to supply a decoder to select which of the devices will get written and another to select which of the devices will get read (ie, output-enabled). The diagram shows how to create an 8-bit-wide '670.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Sorry to go OT here but I just want to mention something about the Retro Stack Exchange site...I have a reputation of over 3100 there. I'm in the top 20 users from about 3900 users overall. Yet, I am personally moving away from using it completely. I just can't get over the hypocrisy of that site. Which goes for all SE sites actually.

Anyway...IM me if you want to know more.

Sorry for the OT...

_________________
Cat; the other white meat.

Nice. About the same number of chips as the 'LS670 solution, but with one disadvantage: the CPU can't "remember" what was written to the latches unless memory locations are used to store copies, which would mean two WRites per bank switch.

This is why I suggested the 74AL996 Read-Back Latch, in my post above.

(Sorry for the delay in responding.)

_________________
"I am endeavoring, ma'am, to create a mnemonic memory circuit... using stone knives and bearskins." -- Spock to Edith Keeler

That's true if there are two different addresses involved. ie - you have to write to the 670 (as a write-only IO device) at one address then write to RAM at some other address. But there's a work-around if you're willing to alter the decoding a little. Just fix it so there's a small portion of the RAM range which activates both devices. (I means writes activate both devices. Reads only activate RAM.)

Those 'ALS996 are kinda cool, despite certain drawbacks. And your schematic looks good. One nit-pick: on reads those chips will drive the data bus throughout the cycle (not just when PHI2 is high), am I right? That'll probably work, but it's a lapse of good practice which affects signal integrity and power consumption (as I recently explained here ). Instead it's best (also quite simple) to observe the convention that nothing drives the data bus when PHI2 is low.

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html