Timing Error with Kowalski Simulator

[8BIT]

I've been working on an application that requires exact cycle counting and have found a small error in the Kowalski simulator.

While the WDC documents are not consistent across many versions of the W65C02 datasheet, it does elude in many that the zero page indirect Y addressing mode will add 1 clock if a page boundary is crossed while computing the target address. I confirmed this using the Visual6502 simulator.

So an LDA (zp),Y instruction will take 5 cycles to complete with no page crossing and 6 cycles if there is a page crossing. The Kowalski simulator calculates 5 cycles regardless of page crossing.

Here is my test code:

Code: Select all

	*=	$1000
	LDA	#$E0		; Load $02E0 into $80
	STA	$80
	LDA	#$02
	STA	$81
	LDY	#$20		; set index to $20
	LDA	($80),Y	; get value at $0300 ($02E0 + $20)
	STA	$82

This is the Visual6502 trace:

Code: Select all

12	000a	b1	1	LDA (zp),Y	000a	02	00	20	fd	nv‑BdIzc
12	000a	b1	1	LDA (zp),Y	000a	02	00	20	fd	nv‑BdIzc
13	000b	80	1					 000b	02	00	20	fd	nv‑BdIzc
13	000b	80	1					 000b	02	00	20	fd	nv‑BdIzc
14	0080	e0	1					 000c	02	00	20	fd	nv‑BdIzc
14	0080	e0	1					 000c	02	00	20	fd	nv‑BdIzc
15	0081	02	1					 000c	02	00	20	fd	nv‑BdIzc
15	0081	02	1					 000c	02	00	20	fd	nv‑BdIzc
16	0200	00	1					 000c	02	00	20	fd	nv‑BdIzc
16	0200	00	1					 000c	02	00	20	fd	nv‑BdIzc
17	0300	00	1					 000c	02	00	20	fd	nv‑BdIzc
17	0300	00	1					 000c	02	00	20	fd	nv‑BdIzc

I know this won't affect many projects, but wanted to share in case someone found it useful.

Daryl

[BigDumbDinosaur]

8BIT wrote:

I've been working on an application that requires exact cycle counting and have found a small error in the Kowalski simulator...The Kowalski simulator calculates 5 cycles regardless of page crossing.

Interesting. I do use the cycle count function now and then, but never noticed this in the past.

[8BIT]

I took a quick look at the source code for the simulator. I'm not positive, but it may not be accounting for ANY page crossing adjustments (except for branches, which do work correctly). It may take some time, but I will try to verify each address mode against the Visual6502 to verify that.

Daryl

[BigDumbDinosaur]

8BIT wrote:

I took a quick look at the source code for the simulator. I'm not positive, but it may not be accounting for ANY page crossing adjustments (except for branches, which do work correctly). It may take some time, but I will try to verify each address mode against the Visual6502 to verify that.

Daryl

Do you have the tools necessary to build a revised version of the simulator?

[Druzyek]

BigDumbDinosaur wrote:

Do you have the tools necessary to build a revised version of the simulator?

That would be great. Maybe we could look at a few of the other bugs in it if someone can build it. Breakpoints for one don't work very well...

[Dr Jefyll]

8BIT wrote:

zero page indirect Y addressing mode [will] add 1 clock if a page boundary is crossed while computing the target address

That's true for LDA ADC CMP and many of the others. But in the case of a write -- STA indirect Y -- the extra clock occurs whether or not a page crossing occurs. An important piece of trivia, especially if someone does dig in and try to fix the simulator.

[8BIT]

BigDumbDinosaur wrote:

8BIT wrote:

I took a quick look at the source code for the simulator. I'm not positive, but it may not be accounting for ANY page crossing adjustments (except for branches, which do work correctly). It may take some time, but I will try to verify each address mode against the Visual6502 to verify that.

Daryl

Do you have the tools necessary to build a revised version of the simulator?

No, not unless there is a free C++ compiler somewhere I can use.

Daryl

[8BIT]

Dr Jefyll wrote:

8BIT wrote:

zero page indirect Y addressing mode [will] add 1 clock if a page boundary is crossed while computing the target address

That's true for LDA ADC CMP and many of the others. But in the case of a write -- STA indirect Y -- the extra clock occurs whether or not a page crossing occurs. An important piece of trivia, especially if someone does dig in and try to fix the simulator.

Note 1 from the instruction timing chart in the WDC 65C02 manual (2004 version) says:
"1. Add 1 cycle for indexing across page boundaries, or write. This cycle contains invalid addresses."

So yes, any write will contain the extra cycle needed to adjust the address pointer. It's just the read instructions that I can see.
So far, [LDA abs, x], [LDA abs, y], and [LDA (zp), y] all need an extra cycle if the page is crossed. [LDA (zp, x)] does not as it wraps back around within zero page. ADC, AND, BIT, CMP, EOR, LDA, LDX, LDY, ORA, SBC all need to be tested. With ADC and SBC, the decimal mode flag also needs to be considered, and I believe the Kowalski simulator adds a cycle correctly.

Daryl

[8BIT]

Druzyek wrote:

BigDumbDinosaur wrote:

Do you have the tools necessary to build a revised version of the simulator?

That would be great. Maybe we could look at a few of the other bugs in it if someone can build it. Breakpoints for one don't work very well...

I have managed to hack together a VC++ tool set and have compiled the 1.2.6 version from the sources. If a couple of you can try to run the attached in your systems, that would help me ensure the tool set is working correctly. I'm a novice with C++ and the whole Windows build environment, so I make no promises to fix anything. I will try to update the cycle counting, once I get them documented better. After that, we can work together to make other changes or enhancements.

Please let me know if this works on your system. Unzip to a any folder. Run the 6502.exe. Load the "min_mon.asm" and assemble and Simulate. Open the Output window and press RST on the tool bar. You should see the EHBASIC start screen. You may need to set the input/output window to $F000.

Daryl

[BigDumbDinosaur]

8BIT wrote:

I have managed to hack together a VC++ tool set and have compiled the 1.2.6 version from the sources.

FYI, the current executable that may be downloaded from Mike Kowalski's website is version 1.2.12. This version fixes several bugs in conditional assembly, listing format and other items. I have contacted Mike via E-mail to see if the source for 1.2.12 is available.

BTW, I downloaded and tried out your compiled version. It appears to be functional and is able to assemble the firmware for POC V1.1, with the only errors coming from conditional assembly bugs that were in versions 1.2.8 and older.

[8BIT]

It would be great if we could get the latest source. Thanks for chasing that down!!

Daryl

[Dr Jefyll]

8BIT wrote:

I will try to update the cycle counting, once I get them documented better.

Be on the lookout for irregularities like this, which almost all documents omit.

Quote:

Table 7-1 of the WDC datasheet [...] claims this issue has been corrected for the CMOS chip. But in fact that's only true regarding ROL ROR ASL and LSR. The fix does not apply to INC and DEC [...]

[8BIT]

Thanks Jeff. I was planning to use the Visual 6502 as a base reference. But, it looks like I may need to consider the 6502/65C02 differences as well when determining cycle adjustments. I will most likely create a table to document all options.

Daryl

[Druzyek]

Would it make sense to make a list of bugs we might be able to fix?

[8BIT]

Druzyek wrote:

Would it make sense to make a list of bugs we might be able to fix?

Sure, but lets wait to see if we can get a more recent source to start with. Some bugs may have been fixed, such as BDD's conditional assembly.

I'm hoping we can get the 1.2.12 source.

Daryl