Overview of 6502-like cores, hard, soft, partial, overblown

[kakemoms]

It all started with the 6502 and 6501 in 1975. The first instruction set is quite well defined except for the fact that ROR was missing.

So the list starts with NMOS hard cores from MOS technology:

MOS MCS6501 (1975) - 1MHz - 150 opcodes, pin compatible with M6800, external clock, 64KB address space, IRQ, NMI , RDY, DBE (Data Bus Enable), BA (Bus Available), VMA
MOS MCS6502 (1975) - 1MHz - 150 opcodes, 64KB address space, IRQ, NMI, RDY pin, SYNC, 2 phase out
MOS MCS6503 (1975) - 1MHz - 150 opcodes, 4KB address space, IRQ, NMI
MOS MCS6504 (1975) - 1MHz - 150 opcodes, 8KB address space, IRQ
MOS MCS6505 (1975) - 1MHz - 150 opcodes, 4KB address space, IRQ, RDY pin

All 1975 models came in a white ceramic package without an external ground strap.

MOS MCS6501 (1976) - 1&2MHz - 151 opcodes, pin compatible with M6800, external clock, 64KB address space, IRQ, NMI , RDY, DBE (Data Bus Enable), BA (Bus Available), VMA
MOS MCS6502 (1976) - 1&2MHz - 151 opcodes (added ROR), 64KB address space, IRQ, NMI, RDY, SYNC, 2 phase out
MOS MCS6503 (1976) - 1&2MHz - 151 opcodes (added ROR), 4KB address space, IRQ, NMI
MOS MCS6504 (1976) - 1&2MHz - 151 opcodes (added ROR), 8KB address space, IRQ,
MOS MCS6505 (1976) - 1&2MHz - 151 opcodes (added ROR), 4KB address space, IRQ, RDY
MOS MCS6506 (1976) - 1&2MHz - 151 opcodes (added ROR), 4KB address space, IRQ, 2 phase out
MOS MCS6512 (1976) - 1&2MHz - 151 opcodes, external clock, 64KB address space, IRQ, NMI, RDY, SYNC, DBE
MOS MCS6513 (1976) - 1&2MHz - 151 opcodes, external clock, 4KB address space, IRQ, NMI
MOS MCS6514 (1976) - 1&2MHz - 151 opcodes, external clock, 8KB address space, IRQ
MOS MCS6515 (1976) - 1&2MHz - 151 opcodes, external clock, 4KB address space, IRQ

Most 1976 models came in a ceramic package, some with and some without an external ground strap. Both white and grey ceramic packages were used. A few early 1977 produced models are in white ceramic packaging, but most were produced using black plastic packaging. Later, only gray ceramic packages were used, but usually only on early new revision runs.

MOS MPS6507 (1977) - CO-10745 used in Atari 2600. No early datasheet found (see below).
MOS MCS6502Z (1980) - IC in 40-pin ceramic package. No datasheet found.
MOS MCS6508 (1981) - IC in 40-pin ceramic package. No early datasheet found (see below).

MOS MPS6510 (1981) - 1&2MHz - 151 opcodes, external clock, 64KB address space, IRQ, AEC (Address/Databus Enable), 256Byte RAM, 8-bit IO port, optional NMI, optional 2nd-phase input.

CSG MPS6508 (1982) - 1,2&3MHz - 151 opcodes, external clock,64KB address space, IRQ, AEC, 256Byte RAM, IO port
CSG MPS6509 (1982) - 1,2&3MHz - 149+2 opcodes#, external clock, 1MB address space, IRQ, NMI, SYNC, AEC pin
# 6509 has a MMU which uses LDA ($ZP),Y STA ($ZP),Y opcodes to access other memory banks (via register $0001)

MOS MCS6510T (1984) - 1&2&3MHz - 151 opcodes, external clock, 64KB address space, IRQ, AEC, 256Byte RAM, 8-IO ports

MOS MPS7501 (1984) - 1&2MHz - 151 opcodes, external clock, 64KB address space, IRQ, RDY, AEC, GATE IN, 7-IO ports
MOS MPS8501 (1984) - 1&2&3MHz - 151 opcodes, external clock, 64KB address space, IRQ, RDY, AEC, GATE ,256Byte RAM, 7-IO ports

MOS MPS8502 (1985) - 1&2MHz - 151 opcodes, external clock, 64KB address space, IRQ, NMI, RDY, AEC, 7-IO ports
MOS MCS8502 (1985) - 1&2MHz - 151 opcodes, external clock, 64KB address space, IRQ, NMI, RDY, AEC, 7-IO ports


After mid-1985, new CSG CPUs seems to be done with HMOS processes:

CSG MPS6510 (1985) - 1&2&3MHz* - 151 opcodes, external clock, 64KB address space, IRQ, NMI, RDY, AEC, 256Byte RAM, 6-IO ports
CSG MPS6510-1 (1985) - 1&2&3MHz* - 151 opcodes, external clock, 64KB address space, IRQ, AEC, 256Byte RAM, 8-IO ports
CSG MPS6510-2 (1985) - 1&2&3MHz* - 151 opcodes, external clock, 64KB address space, IRQ, AEC, 256Byte RAM, 8-IO ports
* Datasheet states 4MHz expected by 1986. The 6510 HMOS was later (1988?) renamed CSG 8500.

CSG MPS R6502 (1985) - 1,2,3&4MHz - 151 opcodes, 64KB address space, IRQ, NMI, RDY, SYNC, 2 phase out
CSG MPS R6503 (1985) - 1,2,3&4MHz - 151 opcodes, 4KB address space, IRQ, NMI
CSG MPS R6504 (1985) - 1,2,3&4MHz - 151 opcodes, 8KB address space, IRQ,
CSG MPS R6505 (1985) - 1,2,3&4MHz - 151 opcodes, 4KB address space, IRQ, RDY
CSG MPS R6506 (1985) - 1,2,3&4MHz - 151 opcodes, 4KB address space, IRQ, 2 phase out
CSG MPS R6507 (1985) - 1,2,3&4MHz - 151 opcodes, 8KB address space, RDY
CSG MPS R6512 (1985) - 1,2,3&4MHz - 151 opcodes, external clock, 64KB address space, IRQ, NMI, RDY, SYNC, DBE
CSG MPS R6513 (1985) - 1,2,3&4MHz - 151 opcodes, external clock, 4KB address space, IRQ, NMI
CSG MPS R6514 (1985) - 1,2,3&4MHz - 151 opcodes, external clock, 8KB address space, IRQ
CSG MPS R6515 (1985) - 1,2,3&4MHz - 151 opcodes, external clock, 4KB address space, IRQ
CSG MCS R65xx (1985) - same as MPS above, but in ceramic package instead of plastic (improved heat conductance).

MOS MCS8502 (1986) - 1&2&3&4MHz - 151 opcodes, external clock, 64KB address space, IRQ, NMI, RDY, AEC, 7-IO ports
MOS MCS8503 (1986) - 1&2&3&4MHz - 151 opcodes, external clock, 64KB address space, IRQ, AEC, 8-IO ports
MOS MCS8500 - See CSG MPS6510

All packages are DIP40 except 65x3-65x7 which are DIP28

Rockwell NMOS instruction set has the basic 151 opcodes plus bit-manipulation instructions (59 opcodes), which gives a total of 210 opcodes. They made most MOS CPU 65xx variants as R65xx (but not 6509), plus a number of microcontrollers and other variants:

R6500/11(1980) - 1&2MH - 210 opcodes, 3KB mask ROM, 16KB ext address space, 192Bytes internal RAM, SYNC, NMI, 1 phase out,4*8-IO ports
R6500/12(1980) - 1&2MH - 210 opcodes, 3KB mask ROM, 16KB ext address space, 192Bytes internal RAM, SYNC, NMI, 1 phase out,7*8-IO ports
R6500/13(1987) - 1&2MH - 210 opcodes, 256Byte mask ROM, 64KB ext address space, 192Bytes internal RAM, NMI, SYNC, 1 phase out,4*8-IO ports
R6500/15(1984) - 1&2MH - 210 opcodes, 4KB mask ROM, 16KB ext address space, 192Bytes internal RAM, SYNC, NMI, 1 phase out,4*8-IO ports
R6500/16(1984) - 1&2MH - 210 opcodes, 4KB mask ROM, 16KB ext address space, 192Bytes internal RAM, SYNC, NMI, 1 phase out,7*8-IO ports
R6501Q (1982) - 1&2MHz - 210 opcodes, 64KB address space, NMI, 192Byte RAM, SYNC, 2 phase out, 4-IO ports
R6511Q (1984) - 1&2MHz - 210 opcodes, 64KB address space, NMI, 192Byte RAM, SYNC, 1 phase out, 4*8-IO ports
R6511AQ(1988?) - 1&2MHz - 210 opcodes, 16KB ext address space, 192Bytes SRAM, NMI, 1 phase out,2*8-IO ports
R65/11EB(1987) - 1&2MH - 210 opcodes, 4KB address space, 192Bytes internal RAM, SYNC, NMI, 1 phase out,4*8-IO ports
R65F11(1987) - 1&2MHz - Forth ROM+210 opcodes, 16KB ext address space, 192Bytes SRAM, NMI, 1 phase out,2*8-IO ports

Many of the R65xxzzyy controllers have internal interrupts and timers. Only external are shown above (RESET excluded).

United Microelectronics Corporation (all NMOS):
UM6502 (1983) - 1MHz - 151 opcodes, 64KB address space, IRQ, NMI, RDY, SYNC, 2 phase out
UM6502A (1984) - 2MHz - 151 opcodes, 64KB address space, IRQ, NMI, RDY, SYNC, 2 phase out
UM6502B (1984) - 3MHz - 151 opcodes, 64KB address space, IRQ, NMI, RDY, SYNC, 2 phase out
UM6502C (1984) - 4MHz - 151 opcodes, 64KB address space, IRQ, NMI, RDY, SYNC, 2 phase out
UM6507 (1983) - 1MHz - 151 opcodes, 8KB address space, RDY, 1 phase out
UM6512 (1983) - 1MHz - 151 opcodes, 64KB address space, IRQ, NMI, RDY, SYNC, DBE (Databus enable), external clock
UM6512A (1983) - 1MHz - 151 opcodes, 64KB address space, IRQ, NMI, RDY, SYNC, DBE (Databus enable), external clock
UM6512B (1983) - 1MHz - 151 opcodes, 64KB address space, IRQ, NMI, RDY, SYNC, DBE (Databus enable), external clock
UM6512C (1983) - 1MHz - 151 opcodes, 64KB address space, IRQ, NMI, RDY, SYNC, DBE (Databus enable), external clock

UM6502E: All UM6502(A/B/C) and UB6512(A/B/C) came in an enhanced timing version with an added "E" to the part number.

Synertek (all NMOS):
SY6502 (1975) - 1&2MHz - 151 opcodes, 64KB address space, IRQ, NMI, RDY, SYNC, 2 phase out
SY6503 (1976) - 1&2MHz - 151 opcodes, 4KB address space, IRQ, NMI
SY6504 (1976) - 1&2MHz - 151 opcodes, 8KB address space, IRQ
SY6505 (1976) - 1&2MHz - 151 opcodes, 4KB address space, IRQ, RDY
SY6506 (1976) - 1&2MHz - 151 opcodes, 4KB address space, IRQ
SY6507 (1979) - 1&2MHz - 151 opcodes, 8KB address space, RDY

SY6512-6515 (1976) - same as SY650x, but with 2phase clock input (no internal clock). The 6512 has DBE (Databus enable) connected to pin 36.

SY6502 and 6512 are DIP40, all others DIP28

Some other manufacturers and CMOS variants:

Western Design Center:
WDC 65C02 (1978) - 1-6MHz+ 212 opcodes, 64KB address space, IRQ, NMI, RDY, SYNC, 2 phase out
+ Later releases up to 14MHz with gate length 0.6um.
WDC 65SC02 (1984?) - 1-6MHz - 170 opcodes, 64KB address space, IRQ, NMI, RDY, SYNC, 2 phase out

California Micro Devices:
G65SC02 (1984) - 1-4MHz^ - 178 opcodes, 64KB address space, IRQ, NMI, RDY, SYNC, 2 phase out
G65SC12 (1984) - 1-4MHz^ - 178 opcodes, 64KB address space, external clock, IRQ, NMI, DBE, SYNC
G65SC102 (1984) - 1-4MHz^ - 178 opcodes, 64KB address space, IRQ, NMI, RDY, BE, SYNC, 2 phase out
G65SC112 (1984) - 1-4MHz^ - 178 opcodes, 64KB address space, IRQ, NMI, RDY, BE, SYNC, 2 phase out
G65SC03-07 (1984) - 1-4MHz^ - 178 opcodes, 4-8KB address space: See MOS6503-6507 for details. 28pin package
G65SC03-07 (1984) - 1-4MHz^ - 178 opcodes, 4-8KB address space: See MOS6503-6507 for details. 28pin package
^ Later up to 6MHz (1996)

Rockwell CMOS:
R65C02/21 (1984) - 1-4MHz - 210 opcodes, 64KB address space, NMIA, NMIB, EMS, 128Byte RAM, SYNC, 2 phase out, 5+2-IO ports

M50747 (1984) - 8MHz## - 69 opcodes## , 8KB ROM, 256Byte RAM (no external bus), UART, 7*8bit IO ports
## Internal clock divisor gives 2MHz performance, Mitsubishi M50740-series are mask programmed microcontrollers. Later named MELPS 740-series which were manufactured in over 600 versions. Rebranded as Renesas 740 Microcontrollers in 2002. A few may access external memory, but most do not.

R65C02 (1987) - 1-4MHz - 210 opcodes, 64KB address space, IRQ, NMI, RDY, 192Byte RAM, SYNC, 2 phase out, 6+2-IO ports

Atari Sally (1987) - 1-4MHz - 151 opcodes, 64KB address space, IRQ, NMI, RDY, SYNC, HALT, 2 phase out

Hudson HuC6280 (1987) - 1.79 and 7.16MHz, 214+ opcodes, 2MB address space ¤, IO port, sound output, special video bus.
¤ Hudson contains an internal MMU which divides memory into 8KB banked units. External address bus is 21-bit. Hudson was bought by Konami.

CSG 65CE02 (1988) - 0-10MHz - 256 opcodes, 64KB address space, IRQ, NMI, RDY, SYNC, 2 phase out
CSG 4510 (1991) - 3.5MHz - 256 opcodes, 64KB address space, IRQ, NMI, RDY, SYNC, 2 phase out

Sunplus SPC81A¤¤ (2000) - 4&6MHz - 69 opcodes(?), 80KB ROM + 128Byte RAM, 2 D/A converters (8-bit), 20-IO ports
¤¤ Sunplus has a full range of controllers that contain 65B02 or 65N02 (Full instruction set), 65R02 (Reduced instruction set) or 65S02 (Reduced instruction set+bit+TAX+TXA). The different controllers are equipped with different amounts of ROM, D/A converters and IO ports. They are often found in toys.

W65C134S (1995) - 8MHz - 212 opcodes, 16MB address space, BE (Bus Enable), RUN, 192Byte RAM, 4KB ROM, 1 phase out, UART, 56(!)-IO ports

16-,24- and 32-bit variants:

Western Design Center:
W65C816S (1984) - 0-14MHz - 255 opcodes**, 16MB address space, VDA (Valid Data Address), VPA (Valid Program Address), VPB (Vector Pull), ABORT, BE, 1 phase out
** Instruction set of 65C02 without bit manipulation plus 76 opcodes with new addressing modes. Instruction $42 is not used for anything, but was set aside for future 2-byte opcodes.
W65C802 - is a W65C816 in a W65C02 pin compatible package; max 64KB RAM external.

Ricoh 5A22* (1990) - 1.79-3.58MHz, 256 opcodes (65C816 core), 16MB RAM external, 8 I/O, NMI, IRQ
* The 5A22 (3.58MHz) was used in the Nintendo SNES console of which 49 million units were produced.

Nintendo SA1 (1996) - 10.84MHz, 256+ opcodes (65C816 core)#, Internal 2KB fast ram, 16MB external, DMA, IRQ
# Not including artimetic functions (divide, multiply, cumulative). Also contain decompression circuit for bitplane graphics. The SA1 was used in many SuperNintendo game cartridges to improve performance.

Soft cores:

W65C816GPMCU (2009) Softcore on LatticeECP2M-50.
W65C02GPMCU (2009) Softcore on Lattice MachXO3-6800; shown to run up to 75MHz.
W65C832PXB (2017) Softcore on LatticeECP2M-50 board for ASIC development. Only business customers. Basically 65C02 or 65C816 cores with a 32-bit register addressing modes included (to increase memory size).

Please feel free to add/correct/comment the list. I will continue to update it when I have time (which is not so often).

[Cray Ze]

Mitsubishi produced hundreds of different microcontrollers with enhanced 6502 cores before merging into Renesas.

Just a quick rundown of the cores used in these microcontrollers. I've listed the number of instructions as shown in the datasheets, this does not represent the total number of opcodes due to the many addressing modes. To get total opcodes means counting them manually, and the 7900 series has over a dozen opcode tables. I'll do a proper count later.

740 Family (8bit) - Enhanced 6502
M50740 series: 69 Instructions
M37450 series: 71 Instructions (M50740 instructions +multiply and divide)

7700 Family (16bit) - Source and binary compatible with 740 family.
7700 Series: 103 Instructions
7751 Series: 109 Instructions (7700 series + six new instructions for signed multiplication/division)

7900 Family (16bit) - Source compatible with 7700/7751 (not binary compatible).
7900 Series: 203 Instructions (some 32bit operations were added, and more, I'll need to investigate)


One more for the list:
The КФ1869ВЕ1 is a soviet era clone of the Mitsubishi M50959 (740 Family)

[jac_goudsmit]

Sorry I don't mean to hijack the thread but I wonder if it might be worth some attention to see/show what the "6800 pin compatibility" of the 6501 was all about. I may be completely wrong here, but I think the big selling point of the 6502 compared to the 6501 (and 6800) was actually that the 6502 has an on-board clock generator which made it unnecessary to have an external clock generator. If you've ever seen the schematics and circuit board of an Apple 1, you will know that it was designed to support a 6800 as well as a 6502, and for the 6800 it needed some extra parts soldered onto the motherboard to generate the clock (again, if I recall correctly).

The bottom line is: I think the 6502 was also sort-of pin compatible with the 6800 (the NC pins on the 6502 corresponded to pins on the 6800 that weren't needed in most computers), but instead of an external clock generator needed for the 6501, you could simply connect a crystal and a couple of capacitors between Phi0 and Phi1. And obviously that was more useful, so (like Chuck Peddle said), the 6501 was never intended to be a long-term product, only as a way to get 6800-users to make the cross-over easier, and MOS had no problem sacrificing it to make the Motorola lawsuit go away. Very clever!

(Maybe an expansion of this would be an idea for a mos6502 post on G+?)

===Jac

[Alarm Siren]

The 6501 was the original product, and it was designed to be 100% pin compatible with Motorola's offering, the 6501 design team having come from Motorola's CPU team en-masse. Motorola inevitably flipped their wig and tried to sue MOS Technology. The result was that MOS Technology agreed to stop selling pin-compatible chips, and the 6502 was born - similar to the 6501 but just different enough that it wouldn't work in a 6800 motherboard and thus wouldn't step on Motorola's toes.

There's actually a rather good table on the Wikipedia article, showing the pin-out differences between the three chips:

Code: Select all

Pin     6800            6501            6502
2       Halt            Ready           Ready
3       Phi1 (in)       Phi1 (in)       Phi1 (out)
5       VMA             VMA             N.C.
7       Bus Available   Bus Available   Sync
36      Data Bus Enable Data Bus Enable N.C.
37      Phi2 (in)       Phi2 (in)       Phi0 (in)
38      N.C.            N.C.            Set Overflow Flag
39      3-State Control N.C.            Phi2 (out)

[BigEd]

Fantastic list! The much more recent SunPlus (?) and I think something from STM (SGS-Thomson) are subsetted 6502 with a register missing.

The extra two instructions from WDC are presumably COP and WDM.

(Jac, it would be most excellent if you could redo your comment as a new thread and edit it down to a link there.)

[kakemoms]

BigEd wrote:

Fantastic list! The much more recent SunPlus (?) and I think something from STM (SGS-Thomson) are subsetted 6502 with a register missing.

The extra two instructions from WDC are presumably COP and WDM.

(Jac, it would be most excellent if you could redo your comment as a new thread and edit it down to a link there.)

If you have any more information on SGS-Thomson, feel free to add it!

The extra instructions on WDC are WAI and STP.

[Cray Ze]

kakemoms wrote:

If you have any more information on SGS-Thomson, feel free to add it!

SGS Thomson "ST7 series" according to the linked page. I looked at the ST7 instruction set and architecture, there are some similarities, but I'm not sure I'd call it a 6502 variant, a cousin perhaps.
http://members.casema.nl/hhaydn/howel/p ... 02_CPU.htm

[BigEd]

Ah yes, that's the one! Similar architecture but different instruction set.
https://en.wikipedia.org/wiki/ST6/ST7

[BigEd]

Calculi found a 6502 core in the GHH393:
viewtopic.php?f=1&t=4603&p=55674#p55674
and the Sunplus SPC81A says it has a core with 69 instructions:
http://datasheet.datasheetarchive.com/o ... 428557.pdf

Quote:

The SPC81A 8-bit microprocessor is a high performance
processor equipped with Accumulator, Program Counter, X
Register, Stack pointer and Processor Status Register (this is the
same as the 6502 instruction structure).

(Note the lack of mention of a Y register!)

See also this thread on the Furby:
viewtopic.php?f=1&t=2027

See also this table from a Sunplus datasheet:

[Cray Ze]

The WDC W65C816S is not on the list yet, I guess I should check that we're including 16bit variants (a bit late after my Misubishi post).
I guess we can put W65C802 on the list as well.

I'll make a few refinements to the Mitsubishi info soon (still gathering data), though I've had a chance to count the opcodes on the 7900 series, scary beast, 849 opcodes.


I also spotted a more up to date version of the sunplus manual here:
http://www.lcis.com.tw/paper_store/pape ... 643789.pdf

[BigEd]

Interesting note:

Quote:

The CPU type 65N02 has two kinds of body, the one uses standard 6502 OP code, the other one uses Sunplus OP code

So, same instruction set architecture, different instruction encoding.

[White Flame]

Huh, so the Sunplus version has bit instructions, but they're different from rmb/smb/bbr/bbs. Instead of the two branch instructions per bit, they have INVert bit and TeST bit. The latter sets Z to the inverse of the bit.

[Tor]

Alarm Siren wrote:

The 6501 was the original product, and it was designed to be 100% pin compatible with Motorola's offering, the 6501 design team having come from Motorola's CPU team en-masse. Motorola inevitably flipped their wig and tried to sue MOS Technology. The result was that MOS Technology agreed to stop selling pin-compatible chips, and the 6502 was born -[..]

The 6501 and the 6502 were born at the same time, they're both in the first data sheet and MOS brought both chips to the first presentation at WESCON in September 1975 (6501 sold at $20, 6502 at $25 - except that they weren't allowed to sell them from the Convention, so they sold chips from a hotel room instead).

[JeeK]

I think nobody mentioned it previously. Wouldn't it be great to have such a list (summed up from the above) on http://6502org.wikidot.com?

[RalfK]

Hi,

what about the 6511? This one is part of an Applebus board manufactured in West-Germany by IBS called AP21 in 1985.



- Ralf