WDC Errata

[Alarm Siren]

Just thought it might be handy to catalogue all the errors I have thus far located in official WDC documentations, in the hope noöne else will be tripped up by the same heffalump traps as I.

In so far as I am able to determine, these are the latest versions of the respective documents, and I'll update this post if/when I find more errors.

W65C02S Datasheet, 11th Nov 2016
Page 29, Table 6-4: TAY, TRB and TSX instructions are all errorneously listed as having a,x addressing mode opcodes. The three opcodes listed actually belong to LDY a,x, LSR a,x and ORA a,x as correctly listed earlier in the table.


Software Development System - Assembler/Linker/Librarian, Sept 2005
Pages 19 & 26: It is stated on page 19 that a label may or must, depending on context, be followed by a colon. The description of Unique Labels on page 26 does not contradict this, however in practice Unique Labels must not be followed by a colon.

Page 37: It is stated that the default output format for the linker is Motorola S19 (-HM19), when infact it is WDC Binary (-HZ).

Page 55: It is stated that "Filenames may also be enclosed in single or double quotes." despite this not being true.

Page 73: "ENDR" is listed as a closing macro for a "REPT" block, which in fact the correct closing macro is "ENDREPT".

[JeeK]

WDC W65C816S 8/16-bit Microprocessor
13 September, 2010
11 November, 2016

• p. 35, Table 5-4 Opcode Matrix

  Code: Select all

  MSB 0, LSB C: TSB: blue
  MSB 7, LSB A: PLY: blue
  MSB B, LSB 2: LDA (d): blue
  MSB *, LSB 6: white
  MSB *, LSB 7: red
  

  Code: Select all

  < blue = new instruction
  > blue = 65C02 + 65802/65816
  < red = Old instruction with new addressing mode
  > red = 65802/65816 only
  

• p. 36, Table 5-5 Operation, Operation Codes, and Status Register

  Code: Select all

  Mnemonic Operation      Opcode          Value
  ADC                     (a)             empty
  AND     A and M -> A
  EOR                     (a,x)           empty
  JSL*
  SBC                     al              EF
  STA                     a,y             99
  TRB      A and M -> M
  

[JeeK]

Programming the 65816

Some typos, but also missing clarfication about some addressing modes.
See also 65816 Addressing modes and cycle counts.

• p. 4, p. 177

  Code: Select all

  < JRS Using Absolute Indexed Indirect Addressing
  --
  > JSR Using Absolute Indexed Indirect Addressing
  

• p. 52, para. 3:
  

  Code: Select all

    In the 6502/65C02, the effective address formed using zero
    page indexed addressing from a zero page base address of $F0 and an
    index of $20 is $10; that is, zero page indexed effective addresses wrap
    around to always remain in the zero page. In the emulation mode this is
  < also true. But in native mode, there is no page wraparound: a direct
    page starting at $2000 combined with a direct page base of $20 and a
    sixteen-bit index holding $300 results in an effective address of $2320.
  --
    In the 6502/65C02, the effective address formed using zero
    page indexed addressing from a zero page base address of $F0 and an
    index of $20 is $10; that is, zero page indexed effective addresses wrap
    around to always remain in the zero page. In the emulation mode this is
  > also true except for 65802/65816 only opcodes or the direct page
  > low byte is not equal zero. But in native mode, there is no page wraparound: a direct
    page starting at $2000 combined with a direct page base of $20 and a
    sixteen-bit index holding $300 results in an effective address of $2320.
  > Note that a direct page access is always limited to bank 0 (wrapping
  > around at $FFFF)..
  

• p. 59, Table 4-6 Major Dofferences Between Processors and Modes
  
  To fix:

  Code: Select all

                          6502    65C02   65802 Native    Emul.   65816 Native    Emul.
  direct page indexed     wraps   wraps   crosses page    wraps   crosses page    wraps
  

  Changes:

  Code: Select all

  < direct page indexed   wraps   wraps   crosses page    wraps   crosses page    wraps
  > direct page indexed   wraps   wraps   crosses page*2  wraps*1 crosses page*2  wraps*1
  --
  > Notes:
  > *1 only for 6502/65C02 opcodes and if direct page register low byte = 0, *2
  > *2 only in bank 0, wrapping around
  

• p. 154 11) Chapter Eleven, The Complex Addressing Modes, Table 11-1
  

  Code: Select all

  < Available on the 6502 and 65816 only:
  --
  > Available on the 65802 and 65816 only:
  

• p. 278, 65802/65816: The Direct Page, para. 2:
  

  Code: Select all

    Pay particular attention to the peculiarities of the direct
    page in the emulation mode: as with the 6502 and 65C02, instructions
    which use direct page addressing modes will _wrap_ to stay within
  < the zero page, but only when the direct page register is equal to zero.
  --
    Pay particular attention to the peculiarities of the direct
    page in the emulation mode: as with the 6502 and 65C02, instructions
    which use direct page addressing modes will _wrap_ to stay within
  > the zero page, but only when the low byte of the direct page register is equal to zero.
  

• p. 283, 17) Chapter Seventeen, The Addressing Modes, para. 9
  

  Code: Select all

  < The exception to this is that zero page stack wrapping is only enforced for
    6502 and 65C02 instructions, and only when DP = 0 in the case of page
    zero wrapping.
  --
  > The exception to this is that zero page _and_ stack wrapping is only enforced for
  > 6502 and 65C02 instructions, and only when DP low byte = 0 in the case of page
    zero wrapping.
  

• p. 317
  
  Quote:

  < Sampler Syntax
  --
  > Sample Syntax

[Alarm Siren]

JeeK wrote:

WDC W65C816S 8/16-bit Microprocessor
13 September, 2010
11 November, 2016

p. 35, Table 5-4 Opcode Matrix

Code: Select all

MSB 0, LSB C: TSB: blue
MSB 7, LSB A: PLY: blue
MSB B, LSB 2: LDA (d): blue
MSB *, LSB 6: white
MSB *, LSB 7: red

Code: Select all

< blue = new instruction
> blue = 65C02 + 65802/65816
< red = Old instruction with new addressing mode
> red = 65802/65816 only

I think that New Instruction / Old Instruction means New to the 65816, i.e. not present in the 65C02. Based on that definition, 0C and 7A should be white as they're present on the 65C02. B2 should be red - it exists on the 65C02 but is the (zp) addressing mode, not the 65816's (d) mode which is technically different (even if it can be thought of as a successor). *6 should be red for the same reason - its d or d,x modes instead of zp and zp,x. Finally *7 should be red as you said.

JeeK wrote:

p. 36, Table 5-5 Operation, Operation Codes, and Status Register

Code: Select all

Mnemonic Operation      Opcode          Value
ADC                     (a)             empty
AND     A and M -> A
EOR                     (a,x)           empty
JSL*
SBC                     al              EF
STA                     a,y             99
TRB      A and M -> M

I'm not actually entirely sure what you're trying to say on that one as the formatting is somewhat unclear. My best interpretation is as follows:

ADC is listed as having an (a) mode and it should not. I don't know for certain if this is correct (having not used the 65816) but it would make sense as no other instruction of this type has an (a) mode, plus the 17 opcode appears elsewhere as ORA [d],y.

AND's operation should be A and M -> A. I agree, though to use WDC's own notation (as listed in note 1 after the table) it should infact be A+M->A.

EOR is listed as having an (a,x) mode when it should not. Again this makes sense for the class of instruction, and the 5D opcode is listed twice.

JSL should have an asterisk to mark it as a new 65816 instruction. Agreed.

SBC should have an opcode listed under the "al" addressing mode, specifically EF. Assuming that the table 5-4 is correct, then this change is also correct.

STA should have an opcode listed under the "a,y" addressing mode, specifically 99. Assuming that the table 5-4 is correct, then this change is also correct.

TRB's operation should be A and M -> M. This is not actually correct for TRB's effect on memory. Instead it should be (~A)+M->M, again using WDC's own notation. This is because TRB clears the memory bits that correspond to ones in A. Without the negation, it would instead clear the bits which correspond to zeroes in A.

[barrym95838]

The use of a + symbol to signify a bit-wise AND is very counter-intuitive, at least to me.

Mike B.

[Alarm Siren]

I agree, but since WDC went to the effort of specifying their syntax I feel we ought to use it for consistency.

[JeeK]

Alarm Siren wrote:

JeeK wrote:

WDC W65C816S 8/16-bit Microprocessor
13 September, 2010
11 November, 2016

p. 35, Table 5-4 Opcode Matrix

Code: Select all

MSB 0, LSB C: TSB: blue
MSB 7, LSB A: PLY: blue
MSB B, LSB 2: LDA (d): blue
MSB *, LSB 6: white
MSB *, LSB 7: red

Code: Select all

< blue = new instruction
> blue = 65C02 + 65802/65816
< red = Old instruction with new addressing mode
> red = 65802/65816 only

I think that New Instruction / Old Instruction means New to the 65816, i.e. not present in the 65C02. Based on that definition, 0C and 7A should be white as they're present on the 65C02. B2 should be red - it exists on the 65C02 but is the (zp) addressing mode, not the 65816's (d) mode which is technically different (even if it can be thought of as a successor). *6 should be red for the same reason - its d or d,x modes instead of zp and zp,x. Finally *7 should be red as you said.

"New Instruction" won't hold however you (or WDC) want to turn it. It's not consistent anyway. It just not appropriate and simply ambiguous. My first try was also to hold on the legend's interpretation I it led to much more failures in coloring. Then I took the other way round and the colors showed me what was really meant.
And the result was:
> blue = 65C02 + 65802/65816
> red = 65802/65816 only
with only some minor fixes in color (apart from 2 columns which has to be swapped).
I would suggest to go with this, because it was also found in "Programming the 65816", p. 436, which uses a dot for blue and a star for red.

Alarm Siren wrote:

JeeK wrote:

p. 36, Table 5-5 Operation, Operation Codes, and Status Register

Code: Select all

Mnemonic Operation      Opcode          Value
ADC                     (a)             empty
AND     A and M -> A
EOR                     (a,x)           empty
JSL*
SBC                     al              EF
STA                     a,y             99
TRB      A and M -> M

I'm not actually entirely sure what you're trying to say on that one as the formatting is somewhat unclear. My best interpretation is as follows:

ADC is listed as having an (a) mode and it should not. I don't know for certain if this is correct (having not used the 65816) but it would make sense as no other instruction of this type has an (a) mode, plus the 17 opcode appears elsewhere as ORA [d],y.

Right, ADC has identical address modes as AND, ORA, EOR, CMP, SBC, LDA from the same instruction class.

Alarm Siren wrote:

AND's operation should be A and M -> A. I agree, though to use WDC's own notation (as listed in note 1 after the table) it should infact be A+M->A.

They wanted to render a logical "and" symbol but used a circumflex, which seem a little wrong to me.
For ORA WDC found the right symbol for the logical "or" symbol. In my opinion it should not rendered as "+", that's not equivalent a logical and (and not very common, not in times where text processing provides symbol tables of all kinds) .

I forgot to mention that EOR has the same notation problem. The proper symbol is missing, instead they used "xv" what ever the meaning of this combination of lowercase characters is, at least not known to me.

Alarm Siren wrote:

EOR is listed as having an (a,x) mode when it should not. Again this makes sense for the class of instruction, and the 5D opcode is listed twice.

It's wrong for this class of instruction. (a,x) is a rare used addressing mode just available for JMP and JSR.

Alarm Siren wrote:

JSL should have an asterisk to mark it as a new 65816 instruction. Agreed.

Right, that was meant.

Alarm Siren wrote:

SBC should have an opcode listed under the "al" addressing mode, specifically EF. Assuming that the table 5-4 is correct, then this change is also correct.

That's indeed correct. I proved it with several assemblers, monitors, emulators and other documentation sources.

Alarm Siren wrote:

STA should have an opcode listed under the "a,y" addressing mode, specifically 99. Assuming that the table 5-4 is correct, then this change is also correct.

That's indeed correct. I proved it with several assemblers, monitors, emulators and other documentation sources.

Alarm Siren wrote:

TRB's operation should be A and M -> M. This is not actually correct for TRB's effect on memory. Instead it should be (~A)+M->M, again using WDC's own notation. This is because TRB clears the memory bits that correspond to ones in A. Without the negation, it would instead clear the bits which correspond to zeroes in A.

You're absolutly right. My correction introduced a new one.

In addition, found an issue for XBA, too.

The table reworked:

Places of change are marked with underscores.

Code: Select all

Mnemonic Operation      Opcode          Value
ADC                     (a)             _empty_
AND     A _and_ M -> A
EOR     A _xor_ M -> A  (a,x)           _empty_
JSL_*_
SBC                     al              _EF_
STA                     a,y             _99_
TRB     _(~A) and M->M_
XBA     B _<->_ A

and ... logical symbol
xor ... logical symbol

[JeeK]

Alarm Siren wrote:

I agree, but since WDC went to the effort of specifying their syntax I feel we ought to use it for consistency.

At least for "Programming the 65816" (see page 433, the opcode table), they don't really have the problem to go with the common logical symbols for AND, OR and XOR operators. And we can see in Table 5-5 of the data sheet for ORA WDC already used the correct symbol, but simply failed to do so for AND and EOR ... (a typographical way).

I think in this case we would keep the consistency (with scope to the document) with the use the proper logical symbols.

[BigEd]

There are mathematical symbols for AND, OR and XOR which bear some resemblance:
AND ∧
OR ∨
XOR can be ⊻ (or in my recollection ⩝)

Which is to say, there's more than one possible convention.

[Alarm Siren]

JeeK wrote:

They wanted to render a logical "and" symbol but used a circumflex, which seem a little wrong to me.
For ORA WDC found the right symbol for the logical "or" symbol. In my opinion it should not rendered as "+", that's not equivalent a logical and (and not very common, not in times where text processing provides symbol tables of all kinds) .

I forgot to mention that EOR has the same notation problem. The proper symbol is missing, instead they used "xv" what ever the meaning of this combination of lowercase characters is, at least not known to me.

Note 1 on page 38, immediately after table 5-5:

Code: Select all

The following are the definitions of the operational symbols used:
+ ADD, ^ AND, xv Exclusive OR, * Multiply, ~ NOT, v OR, - Subtract

... I was about to write something about how I was right and you were wrong (I acutally got half way through typing it!), but upon re-reading it I realised that I actually misread the note myself and, infact, it SHOULD be a circumflex in the AND operation, so we're both wrong. Since they went to the trouble to specify the syntax they were using, and by that syntax what they wrote is entirely correct, we ought to respect it. Same goes for xv for Xor. As BigEd says, there's more than one way of writing logic symbols.

Jeek wrote:

with scope to the document

From the scope of this specific document, since it explicitly defines the symbols, those are the one we should use. The other document (which I have not read) has no bearing on the matter, even if the symbols used there are more conventional.

[JeeK]

Alarm Siren wrote:

...
Note 1 on page 38, immediately after table 5-5:
...
From the scope of this specific document, since it explicitly defines the symbols, those are the one we should use. The other document (which I have not read) has no bearing on the matter, even if the symbols used there are more conventional.

Thanks, that was it. Overlooked it entirely. The big V in ORA looked like a symbol for me and if one wants to be picky about this, the foot note denotes "v" (small V) as OR operator and in that manner at least the ORA has a typographic error.
However, maybe we can agree finally at least on this:

Places of change are marked with underscores.

Code: Select all

Mnemonic Operation      Opcode          Value
ADC                     (a)             _empty_
EOR                     (a,x)           _empty_
JSL_*_
SBC                      al             _EF_
STA                      a,y            _99_
TRB     _~A ^ M -> M_
XBA     B _<->_ A

[Dr Jefyll]

Thanks for pursuing this, guys. Too bad errors are so common in WDC doc.

Are you aware there's another errata collection at http://6502org.wikidot.com/errata-datasheets-w65c816s ?

It would be nice to have all the info in one place. Of course the best place would be in a new, corrected edition from WDC!

-- Jeff

[BigDumbDinosaur]

Dr Jefyll wrote:

Thanks for pursuing this, guys. Too bad errors are so common in WDC doc.

Are you aware there's another errata collection at http://6502org.wikidot.com/errata-datasheets-w65c816s ?

It would be nice to have all the info in one place. Of course the best place would be in a new, corrected edition from WDC!

Funny you mention it, as the info at the 6502 wiki was brought to WDC's attention several times. I'm guessing no one there had time to read it.

[Alarm Siren]

W65C22 Datasheet, 13th Sep 2010
Page 36, Section 3.9: Small typo where "CA1, CA2, DB1, CB2" should be "CA1, CA2, CB1, CB2".

[Rob Finch]

On the W65C816S data sheet dated March 2000, page 16 section 2.6 talking about interrupts states that the processor only saves the program counter high, low, and status register. But later in the document in a table it shows the processor also saving the program bank register during interrupt. So it seems a little inconsistent.