Dr Jefyll wrote:
DerTrueForce wrote:
They will probably be of great use to me, although not for hardware waiting loops like the ones I'm using at this stage.
From personal experience I can tell you hardware waiting loops are a
great way to benefit from the BBS/BBR instructions!
And SMB/RMB are terrific for bit-bang outputs. However, only a minority of 65xx systems map their I/O into zero-page. Sometimes there are good reasons for that; other times it represents a missed opportunity. For further discussion see
major speedup with 65C02 I/O mapped into zero-page.
An alternative might be to be to use BIT - if the status bit you are interested is either bit 6 or bit 7, you can use BIT followed by BMI/BPL or BVS/BVC, rather than LDA followed by AND and then BEQ/BNE.
I've been working with CHOCHI lately, and the status register on the CHOCHI has RX_READY as bit 6, and TX_FULL as bit 1. So, polling for received character can be coded as
Code:
getchar: BIT $C009
BVC getchar
LDA $C008
RTS
By making a trivial change to UART.v, you can code putchar as
Code:
putchar: BIT $C009
BMI putchar
STA $C008
RTS
Without this change, you would have to do something like
Code:
putchar: PHA
putch1: LDA $C009
BPL putchar
PLA
STA $C008
RTS