how can i find info about dma techniques with 6502?
thanx all!
dma and 6502
This will sound silly, but datasheets are your best bet. If the 6502 you're using doesn't have any kind of DMA facility on-chip, then you can simulate it by:
1) Holding phase-2 low (IF AND ONLY IF your 6502 is a static design; if it's a dynamic design, this will not work) will stop the processor dead in its tracks. Then, you can use external bus transceivers to tri-state the address, data, and some control bus signals once the CPU is suitably halted.
2) If you're using an older (dynamic logic) 6502, then you can also hold RDY in a negated state, to halt the processor on the next READ cycle (this applies also to opcode fetch). The disadvantage is that this won't work on WRITE cycles, due to how the older 6502s worked. This wasn't much of an issue in practice, however -- the Commodore 64's DMA engine worked by simply negating RDY, waiting 6 clock cycles to allow any write cycles pending to complete, then disabling bus transceivers.
You'll find modern 6502 implementations to be more accomodating to DMA, especially Western Design Center's chips. Their chips are not only DMA friendly, but also static designs.
1) Holding phase-2 low (IF AND ONLY IF your 6502 is a static design; if it's a dynamic design, this will not work) will stop the processor dead in its tracks. Then, you can use external bus transceivers to tri-state the address, data, and some control bus signals once the CPU is suitably halted.
2) If you're using an older (dynamic logic) 6502, then you can also hold RDY in a negated state, to halt the processor on the next READ cycle (this applies also to opcode fetch). The disadvantage is that this won't work on WRITE cycles, due to how the older 6502s worked. This wasn't much of an issue in practice, however -- the Commodore 64's DMA engine worked by simply negating RDY, waiting 6 clock cycles to allow any write cycles pending to complete, then disabling bus transceivers.
You'll find modern 6502 implementations to be more accomodating to DMA, especially Western Design Center's chips. Their chips are not only DMA friendly, but also static designs.
kc5tja wrote:
This ) Holding phase-2 low ...
Code: Select all
___
/ __|__
/ / |_/ Groetjes, Ruud
\ \__|_\
\___| URL: www.baltissen.org
No, it must be held low.
The 6502's bus tenure is broken into two phases: phase 1 (clock low) and phase 2 (clock high).
Phase 1 is when the CPU combinatorially computes the next bus state. Phase 2 is then it samples the bus state for the next cycle.
Therefore, phase 1 is, essentially, a wasted half-cycle from a data transfer point of view. This is why Commodore, Atari, Apple, et. al., all interleave video and CPU accesses to RAM, with video occuring during phase 1, and CPU during phase 2.
Thus, to delay the CPU for an indefinite amount of time (again, this is all assuming static logic), one can hold the CPU's clock low -- thus elongating phase 1 of the bus cycle.
The 6502's bus tenure is broken into two phases: phase 1 (clock low) and phase 2 (clock high).
Phase 1 is when the CPU combinatorially computes the next bus state. Phase 2 is then it samples the bus state for the next cycle.
Therefore, phase 1 is, essentially, a wasted half-cycle from a data transfer point of view. This is why Commodore, Atari, Apple, et. al., all interleave video and CPU accesses to RAM, with video occuring during phase 1, and CPU during phase 2.
Thus, to delay the CPU for an indefinite amount of time (again, this is all assuming static logic), one can hold the CPU's clock low -- thus elongating phase 1 of the bus cycle.
kc5tja wrote:
No, it must be held low. ...
Code: Select all
___
/ __|__
/ / |_/ Groetjes, Ruud
\ \__|_\
\___| URL: www.baltissen.org
As far as I know, the CMOS version of the 6502 (and W65C02 in particular) has always been a static logic design, so it's always been more flexible with its clocking.
The NMOS variants were definitely dynamic logic though, as I remember several chips having minimum frequencies and duty cycle requirements (including chips from Commodore). It never made sense to me why minimum clock frequencies were imposed until I learned about the differences between static and dynamic logic.
The NMOS variants were definitely dynamic logic though, as I remember several chips having minimum frequencies and duty cycle requirements (including chips from Commodore). It never made sense to me why minimum clock frequencies were imposed until I learned about the differences between static and dynamic logic.
-
GARTHWILSON
- Forum Moderator
- Posts: 8775
- Joined: 30 Aug 2002
- Location: Southern California
- Contact:
The Rockwell, CMD, etc. 65c02's had a maximum phase-2-low time, but could hold phase 2 high indefinitely. WDC made it so you could hold it in either state as long as you want, and put the "S" at the end of the part number to mean "static". The NMOS ones had maximum times for both, so there was no way to run the clock below something like 100kHz regardless of duty cycle.