I think this would be a good bus to base a large scale 6502 computer around, even though the 6502 was left out of the specification because it doesn't halt on memory writes (The 65C02 doesn't have this problem). Because it has 20 address lines an MMU could be included in the system.
I don't have easy access to Eurocard prototype boards so I use 100x155mm stripboards for any Eurocard I want to make (it's a close enough compromise). This is what I used for my 8080 project. I didn't use the STEbus for it because I didn't know of its existence when I designed the bus.
More information is at http://en.wikipedia.org/wiki/STEbus and http://www.howell1964.freeserve.co.uk/Arcom/STEbus.htm
The pinout doesn't describe the Command Modifier lines so I'll put them here (they're elsewhere on the site)
Code: Select all
CM2,1,0
1 1 1 memory read
1 1 0 " write
1 0 1 I/O read
1 0 0 " write
0 1 1 acknowledge
0 1 0 )
0 0 1 )reserved
0 0 0 )
). I imagine the bus transfers are asynchronous like the VMEbus, judging from the CM lines.I think it would be tricky to get the acknowledge signal on the 6502's side correct, because if it enters a wait state for each bus transfer it would half the execution time. I've looked into the 68000 processor which uses an asynchronous bus and the acknowledge signals on various SBC's are tied to the /CS pins of the RAM/ROMs (ANDed together), so I think it would be possible to attach a flip flop to one of the phase outputs of the 6502 (probalby phase-1) which, if it doesn't receive an acknowledge within the clock cycle, halts the CPU.
Any comments are welcome.
Thrashbarg.
