DRAM: How does one generally generate CAS & RAS signals?

[LIV2]

I have no plans to use DRAM but am curious as to how these signals were usually generated in early 6502 systems?

I'm guessing the following are ways you might do it:
1: RC Delay
2: Delay using logic propagation delays
3: Feed a high speed clock into some kind of state machine & divide clock down for PHI2.

Sorry if this is a silly question, I'm having a hard time trying to find any circuit examples etc online.

[AldoBrasil]

In the 6502 era there was no cas/ras scheme, this is post a 1990 thing, mainly from PC world (SDRAM).

Edit:

Answer below tells me that RAS/CAS was indeed used during this time...

Whats the porpuse of it ?

I tought RAS/CAS was an addressing scheme to decrease the ever increasing number of address pins that would be needed for ever increasing RAMs...

[Rob Finch]

Try looking at schematics for the AppleII or Commodore PET / series computers.
AppleII Redbook page 143 has a RAS/CAS generator based on a shift register.

Usually a combination of clocked logic along with logic propagation delays is used. I've not seen an RC implementation.

[GaBuZoMeu]

AldoBrasil wrote:

In the 6502 era there was no cas/ras scheme, this is post a 1990 thing, mainly from PC world (SDRAM).

Edit:

Answer below tells me that RAS/CAS was indeed used during this time...

Whats the porpuse of it ?

I tought RAS/CAS was an addressing scheme to decrease the ever increasing number of address pins that would be needed for ever increasing RAMs...

Dynamic RAM was ways cheaper than static RAM and draws less power. The drawback was the more difficult handling (unless using a Z-80). When 65Kx1 devices became affordable you could expand your memory up to the limit with just 8 small (16 pin IIRC) devices and some glue logic.

The RAS/CAS scheme was used to address the memory (obviously) and to do refreshes with RAS only. So only 256° RAS-only cycles (65K devices) were necessary for complete refresh of all 65K every 2 ms. (°: Some 65K dyn. RAMs like MCM 6665, required only 128 RAS refresh cycles as the 16K ones needed).

[GARTHWILSON]

GaBuZoMeu wrote:

Dynamic RAM was ways cheaper than static RAM and draws less power.

Cheaper, yes; but lower power? Can that be true? Even in the mid-1980's I observed, in my work, an 8Kx8 SRAM holding its data over 16 hours on a 10uF capacitor, with no other source of power. When operating, the entire 65c02 computer, including LCD, took 2mA. (This was at 170kHz to save battery power in an application that didn't need performance).

[BigDumbDinosaur]

GaBuZoMeu wrote:

Dynamic RAM was ways cheaper than static RAM and draws less power.

Cheaper, yes. Lower power consumption, not necessarily. SRAM draws little current when idle, meaning when /CE is not asserted. The Cypress CY1049 512KB SRAM I use in POC V2 consumes 50 milliwatts when idle.

DRAM itself doesn't use a lot of power but when you factor in the need for the constant refreshes, the power consumption picture isn't quite as rosy as it appears to be.

[GaBuZoMeu]

Lower power compared to NMOS (or HMOS) static RAM. CMOS power consumption is proportional to its clock frequency. Stopped only leakage currents but at full speed around 40mA. (2Kx8 about 35mA max. and the early 8Kx8 around 45mA). Dynamic RAMs draw "active" 45mA (65Kx1) and 5mA during "standby" - where "standby" couldn't last long. So CMOS wins when ever speed is not required.

And sorry - I was talking about RAMs during 198x - comparing todays technologies with whats going on back then is something different.

off topic:
I just take a look at some advertising in Elektor 3/1983:
6502: 16,-DM, 6502A: 22,-DM, 6116-LP3: 20,-DM, 4164-150: 21,50 DM, 68000/4: 260,-DM ... playing with µPs wasn't really cheap that days...

[AldoBrasil]

I know that DRAM was cheaper than SRAM (1 transitor vs 6 for sram). But I am not talking about this. RAS/CAS allows, for example, to have 8 bits address pins, because you can do :

Code: Select all

put 8 bits row in the bus.
strobe RAS
put 8 bits column in the bus.
strobe CAS.
8+8 = 16 bits, so you can address 64kb of DRAM using only 8 pins for address.

Modern DRAMs can do more, because usually rows and columns address blocks of ram (pages) not singular 8 bit words.
Lets now suppose that each page has 512 bytes, and the address bus has 8 bits.

Code: Select all

8 bits row on the bus
strobe RAS
8 bits column on the bus
strobe CAS
512 bytes come out of the RAM synchronized by a clock.

voilá, 32mb of ram with a 8 bit bus (more if you use multiple ICs, like done in PC memory - this also allows for more than 8bits per clock - like the usual 64bits or 128bits of current memory channel system).

But this only makes sense if :

• 1 - You have a synchronous DRAM (in other words SDRAM).
  2 - You have too much ram for a bus (you would need 25 bits address bus - even if databus is multiplexed with the address bus - to
  address the same 32megabytes).
  3 - You have a cache to allow the processor to access individual bytes within a page*

*might not always be true.
This is not true for 6502 era computers, thats why I said that there was no RAS/CAS in the era. I am surprised to know that there was indeed RAS/CAS addressing system in the era...

[Rob Finch]

I'm waiting to see if DRAM comes out with yet another xAS signal in order to reduce the number of pins required for addressing.
4Gib DRAMS need 32 bit addressing. This could be 10-11-11 rather than 16-16.

[AldoBrasil]

Now and then 3d memory modules appears in the market. I believe those would have a floor access strobe to select a chip among others...

[LIV2]

Rob Finch wrote:

Try looking at schematics for the AppleII or Commodore PET / series computers.
AppleII Redbook page 143 has a RAS/CAS generator based on a shift register.

Usually a combination of clocked logic along with logic propagation delays is used. I've not seen an RC implementation.

Thanks, it kinda makes sense to me now. and makes me glad I can just use SRAM.