I verified the contents of the ROM against the listing. The part from Reset up to the baudrate detection seems to be identical.

The baudrate detection syncs to the lowspeed timer 1. The clock is 32768 Hz. When T1 reaches 0 the fast clock is used to DEX X from $1000. This is $1000 x 5 fast cycles. Then T1Clo is read and compared against two tables, one for maximum values, one for minimum values.

Now for verification:
($1000 x 5 / 1843200) x $8000 = $016C. As the counter decrements => $100-$6C = $94. The ROM tables have $92 as minimum and $97 as maximum.

($1000 x 5 / 2457600) x $8000 = $0111. As the counter decrements => $100-$11 = $EF. The ROM tables have $EE as minimum and $F2 as maximum.

($1000 x 5 / 3686400) x $8000 = $00B6. As the counter decrements => $100-$B6 = $4A. The ROM tables have $48 as minimum and $4D as maximum.

($1000 x 5 / 4915200) x $8000 = $0088. As the counter decrements => $100-$88 = $78. The ROM tables have $77 as minimum and $7B as maximum.

($1000 x 5 / 6144000) x $8000 = $006D. As the counter decrements => $100-$6D = $93. The ROM tables have $0A as minimum and $12 as maximum - WHICH ARE TOTALLY WRONG.

Contrary to my first verification the compare against the table values is successful for all frequencies but 6,144MHz. If the first comparision against max exits too early, the following compare against min correct this.

I have also verified that 4,9152MHz is running correctly - I did use 4,194304MHz erroneously. Mea culpa. I could also verify that 1,8432MHz works.

The upper frequency limit of my board seems to be 18,432MHz. At least using the crystal osc circuitry without further trimming. 20 and 22,1184MHz did oscillate but the program failed to work. This may also happen because the duty cycle of PHI2 was somewhere between 33/66 .. 40/60.

Next check will be program execution out of flash-eprom. The 39SF010 should arrive soon.

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edit(1): T1L corrected to TIClo, added try with 1,8432MHz

Well, the Flash Eproms (SST39SF010A-55-4C-NHE) arrived and one of them is socketed now.

With my simple loop (lda along, xor #$FF, sta along, bra) running out of the flash, I have tested 11,0592MHz and 14,7456MHz (3x / 4x regular speed).

I couldn't see anything that alerts me. MEMOEB is about 8ns lagging PHI2, this should be OK.

So the next big problem I now have is to choose running the board with 11 or 14MHz

That lag would make sense, but shouldn't sink your attempts to ramp up Ø2.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Today I got a quote from Mouser about the W65C265 in QFP (I asked them to do so.)
Well, now it's online: http://www.mouser.de/ProductDetail/Western-Design-Center-WDC/W65C265S8QG-8/?qs=%2fha2pyFaduiOhbbY1rHwnDzOip%252bR1dfmCie8WPCA%252b8%2fOqgkXJD5k3A%3d%3d