Question About Absolute Addressing

[CitizenSnips]

I'm currently writing a VHDL 6502 core for an FPGA. I'm trying to stay as true to the original microarchitecture as possible in my design, and have been using this block diagram to do so. I'm currently working on the control logic for implementing absolute addressing. I have PCL, PCH, ABL, and ABH registers, as shown in the block diagram. However, I'm unsure as to how I should "save" the lower byte of the effective address used in absolute addressing. I can't hold it in ABL, since I need to load that with the incremented value of PC to retrieve the upper byte of the effective address on the next cycle. I could simply create another intermediate register to hold the lower byte, but I'm wondering how the original 6502 handled this issue before I go changing the microarchitecture, as I'm not gleaning anything from looking at the block diagram. Anyone here know?

[BigEd]

It's often useful to look at some traces in visual6502.

Here we see that the LSB (the first operand byte) passes through the ALU:
http://www.visual6502.org/JSSim/expert. ... 22ad1122ea

So there's your answer - values can take a trip through the ALU to be safe for a cycle.

Edit: I couldn't get to your image link, but I assume you're using Donald Hanson's block diagram.
http://visual6502.org/wiki/index.php?ti ... ck_Diagram

[GARTHWILSON]

I don't know the answer; but although tedious, it may be helpful to see how others have done it:

• links to 19 free HDL 65xx cores http://6502.org/homebuilt#HDL
• comparison of many HDL 6502 cores available (forum topic, with links) viewtopic.php?f=10&t=1673
• BMOW tiny 6502-like CPU in CPLD http://www.bigmessowires.com/cpu-in-a-cpld/
• links to more help understanding the innards of the 6502 at the gate and transistor level viewtopic.php?p=48951#p48951

(These are from the "65-family processors, history, HDL, emulators" section of my links page which has hundreds of 6502 links.) Edit: I see Ed posted while I was writing.

[BigEd]

Thanks Garth - extra pointers always helpful!

[CitizenSnips]

Thanks very much, both of you!

[BigEd]

Good luck with your project - do post updates as you make progress!

[Dr Jefyll]

CitizenSnips wrote:

I'm trying to stay as true to the original microarchitecture as possible in my design, and have been using this block diagram to do so.

Best of luck with your project!

If you haven't already, you should consider the bidirectional nature of the two sets of pass MOSFET's. An actual 6502 exploits the MOSFET's ability to pass a signal in either direction (as can be seen if you explore various visual6502 simulations).

Directly implemented in silicon, the pass transistors are a shortcut that simplifies the design. Unfortunately that's not the case in the FPGA context. This isn't intended to discourage you. I'm just pointing out that using the original 6502 as your roadmap may drastically complicate matters, contrary to what one might expect.

AFAIK only one of the 19 cores in Garth's list models the pass transistors; all the other cores use unidirectional signal paths, which of course map much more easily to FPGA. The exception is Andrew Holme's core, which he describes here and which is the subject of this forum thread.

(BTW, CitizenSnips, it's not necessary to use third-party sites for posting images. On this forum you have the option of including images as attachements to your post. )

cheers,
Jeff

[barrym95838]

Dr Jefyll wrote:

... (BTW, CitizenSnips, it's not necessary to use third-party sites for posting images. On this forum you have the option of including images as attachements to your post. )

cheers,
Jeff

... as a spammer did early this morning (UTC-8) with much vigor, until Garth or Ed chopped him or her off at the ankles. Thanks, guys, I like to keep my porn in a separate frame of mind.

Mike B.