Vulcan-6502 Reloaded has now become real.
I had a full day to test some of the new design ideas, and so far everything has worked as planned.
Choosing to go from 8 colors to 4096 colors required the data bus to grow from 8 bits to 16 bits all the way around.
There are 2 ways to get a 16 bit SRAM : using actual 16 bit SRAM, or by doubling up on 8 bit SRAM. I chose the later.
A series / parallel configuration to create a 1MB x 16 SRAM.SRAM can be connected with the data bus in series or parallel to create just about any configuration.
Four 256K x 16 SRAMs make up a 1MB x 16 memory when their CE lines are tied together with a 2-4 decoder.
In my case, I paralleled the address busses on two 512K SRAMs, and then used their data ports in series.
I then tied their CE lines with an inverter so that I had a 20 bit address bus and a 16 bit data bus (1MB x 16).
I would have purchased new 256K x 16 SRAM is I didn't already have a full tray of 10ns 512K x 8 SRAMs available.
In the end, both methods offer the same result anyhow. Actually, there are benefits to using the 512K x 8 SRAMs.
Going to 16 bits from 8 bits was a huge change to the entire board, which is why I started from the beginning.
Even the final output to the resitor DAC had to fatten up, as color uses 12 of the 16 available bits.
For 12 bit of color (4096 colors), the number of latches and buffers must double.The new 12+1 bit color space is RRRR-GGGG-BBBB-A, which means 4 bits for each primary color, and 1 bit for invisible pixels.
In the original design, the 8 bit color space was just RRR-GGG-BB, so a single 74HC574 or 74HC245 could handle the bus.
Now I will require double the number of ICs to pass the data bus around, and 12 resistors for the DAC rather than just 8.
The photo above shows the color bits as being Red, Green and Blue wires.
To "sync" up the blanking time with the pixel clock, color bits are ANDed with the pixel clock using the 74HC08 AND gates.
After syncing the bits through the AND gates, they are then driven out to the DAC through the two 74HC574 registers.
This system has worked perfectly in all previous designs as well. Even a 1ns delay between blanking and pixel is highly noticeable on the screen!
Testing the new DAC and timing on the monitor.After doing some successful testing with 640x480 resolution, I decided that 400x300 resolution was better for a game system.
The main goal is to deliver high speed Sprites and Images, and at 640x480, the number of pixels per screen is so much larger.
Although the VGA Generator worked perfectly at 640x480, the amount of SRAM required was huge, and the frame rate was much lower.
Now that I have 4096 colors instead of only 256, the image quality will stlll be much better, so I settled back to 400x300 resolution.
As shown above, the monitor had no problems with 640x480, although I would say this is the upper limit for 74HC logic!
In the new design, the X/Y counters are cloned 3 times.Another huge design change I made was in the way that the Sprite Generator and VGA Generator share access to the Video Memory.
Video Memory consists of 2 swappable banks. One is being drawn to screen while the other is accessible by the GPU hardware.
In the previous design, the VGA Generator and GPU fed into a large bank of 74HC245s that created a massive bus switcher.
One set of 245s drove the 20 bit address bus and 8 bit data bus to the Live Buffer with the other drove the Back Buffer.
This certainly worked well, but the resulting pathway had an extra 10 nanoseconds of travel to make it through the gates.
in the new design, I realized that I didn't actually need any of the 245s, as I could just make use of the OE function on the counters.
So now I have 3 sets of X/Y counters, each of them synced together from the master 20MHz Pixel Clock.
Here is how this works...
Counter Set One : Drives the 74HC688 comparators in order to generate the Video Signals. Counters are tapped so that they divide by 4.
Counter Set Two : Drives Video Bank One directly so that when this bank is "Live", it is drawn to the screen.
Counter Set Three : A mirror image of Counter Set Two. Only one can be active at any time. The other is disabled by OE (tristated).
So when one of the Pixel Driving Counter Sets is disabled, the GPU gets access to that Video Bank, since it is now the "Back Buffer".
Having shaved about 10ns of the path means that I can push the Sprite Generator up even more when I get started on the design.
The Data Bus Switch is now 16 Bits Wide.The Data Bus Switch is also double the width. These are just 74HC574s that feed into the Video memory Banks.
Although the system would be capable of displaying true 16 bit color, I am only using 12 bits for color.
The other 4 bits are used internally to speed up the Sprite Generator. I guess they could be considered "micro-code".
Here is how all 16 bits are going to be used in the new design...
Code:
Bit 00 : Red Color Bit 0
Bit 01 : Red Color Bit 1
Bit 02 : Red Color Bit 2
Bit 03 : Red Color Bit 3
Bit 04 : Green Color Bit 0
Bit 05 : Green Color Bit 1
Bit 06 : Green Color Bit 2
Bit 07 : Green Color Bit 3
Bit 08 : Blue Color Bit 0
Bit 09 : Blue Color Bit 1
Bit 10 : Blue Color Bit 2
Bit 11 : Blue Color Bit 3
Bit 12 : Alpha (Invisible) Pixel
Bit 13 : Wrap X Counter Logic
Bit 14 : End of Sprite Data
Bit 15 : Not Used
In the old design, the Alpha Color was detected by feeding the Data Bus to a 74HC688 comparator, which then fed an inverter, FlipFlop.
Alpha Detection was the bottleneck in the old Sprite Generator, and now there is no delay at all!
The X/Y box logic in the Sprite Generator will also be driven by the special bits, so it will also run at maximum speed.
I am hoping to get 10MHz out of the new Sprite Generator, which will by a 3x speed increase over the previous version.
Connecting the Counter Chains to the Video Memory.One of the most time consuming aspects of bread-boarding a 16 bit, high speed Video Game System is... so many wires!
In the photo above, I have connected the switchable address counters to the double Video Memory Banks.
Connecting the Data Bus Switches to the Video Memory.When the counters to the left of the SRAM are active, the 74HC574s to the right are disabled, and the opposite is true for the other bank.
The photo above shows the 12 Data Lines that feed into the Video Memory Bus Switch.
Only 12 bits ever reach the Video Memory, since the other 4 special bits are used internally by the Sprite Generator.
The completed Dual 12 Bit Switchable Data Bus.As you can see, I always use Blue wires for Data Lines, and White wires for Address Lines.
Brown wires are control lines, and the VCC and Ground connections are Red and Green.
The single Brown wire shown heading into the Bus Switch controls the SRAM Write Enable Line.
I feed this through the 574 chain so that WE is registered in sync with any data to be written to the back buffer.
Adding a Switchable 18 Bit Address Bus.The six 74HC574s shown above will create a switchable 18 bit address bus into the double buffered Video Memory.
The address is split into X (9 Bits) and Y (9 Bits), since the addressable box is 400 x 300 pixels.
Just like the 574s the swap the Data Bus, these 574s do the same with the incoming Address Bus from the GPU.
This switch works along with the Counter Switch, making sure only opposing sets are active.
The Complete Address and Data Switch into the Video memory.Did I mention that this type of prototyping requires a LOT of wires??
I cut every single wire to the required length by hand, and then bend them into shape for a neater appearance.
Does it really matter if the final wiring looks neat?... it does to me!
Perhaps this careful planning of wiring is why my breadboard can run reliably up to 32MHz? Who knows!
The New 4096 Color Video Generator is now ready for testing..The only part of the entire design that remains original are the bottom left 2 rows of X/Y comparators.
Everything else is completely redone, and rewired from scratch.
The photo above shows the bare-bones VGA Generator along with the input switch that the GPU will connect to.
For testing, I put my 6502 simulator (AVR 1284) back on the board and loaded it with a 12 bit image.
The AVR pretends to be a 6502 by emulating the address, data, and RW lines of a 6502.
Using the AVR for testing is nice because I can directly load it from the PC, and it has 128K of internal EEPROM space.
Now that an image takes up twice the memory, I cannot even hold a full 400x300 image, as this would require 240K of space.
Later, this will not be an issue, as the external "Cartridge" will be capable of megabytes of data.
Now for some real image testing. At this point, I did not even know if the new 4096 color VGA Generator would work!
A 12 Bit Palette image to be used for testing.I found a nice bitmap showing a 12 Bit Color Palette online, and saved it as a 300x200 image from Photoshop.
There as certainly a much richer variation of colors in the palette when compared to the limited 256 (8 bit) palette.
I also recoded my Sprite Converter Program to handle the conversion of 24 bits to 12 bits.
This program takes any Bitmap and then spites out assembly or C data that can be store in a micro-controller.
4096 Colors looking great on the new Vulcan-74 VGA Generator!it was a pleasant surprise to see the new Video Generator come up for the first time and display an almost perfect representation!
The monitor reported 800x600, which is what my timing is generating, and the colors looked the same as on the original PC image.
The random pixels shown around the image are there because an SRAM contains random data when it is initially powered up.
Proof that 4096 colors could be displayed has now been confirmed!
Another image to be converted and displayed.The color palette looked so good that I needed to try a previous image so I could compare the difference.
The image above was displayed on the old version using only 256 colors, and it still looked pretty good.
Most of the small variations in color shades were lost though, and the image almost looked "posterized".
As you can see in the 24 bit original, the image is perfect as seen on the PC monitor.
Vulcan-74 displaying a very clean 12 bit image.When converted and loaded through the 6502 simulator, the resulting image looked great.
There is no comparison... 4096 colors blows 256 colors away by a huge margin.
The image being displayed on Vulcan-74 looks almost as good as it does on my PC monitor.
Not bad... 12 resistors doing the job of a $300 video card!
For my next test, I will be wiring up another 8 SRAMs in order to create a 2MB x 16 Sprite memory.
If I can get the Sprite Generator to run beyond 4MHz, then Vulcan-74 is going to have unreal power.
Even when it could only do 4MHz Sprites with 256 colors, it did a great job, so the new version is going to be insane.
The Sprite Generator is by far the most complex part of this project, so there will be many more photos coming.
I will report my progress... good or bad! So far it has been all good.
Cheers!
Radical Brad