Sorry for unexpectedly bumping in: I just noticed
an old posting about PHI2 and WDC parts
when following
Jeff's link in the Newbie's section of the forum:
In other words, WDC does not recommend the use of PHIO1 and PHIO2 in new designs.
You should also consider the fact that PHI1O and PHI2O lag Ø2 by an amount that is not specified.
To be more precisely:
In the datasheets of most of the 6502 manufacturers, bus timing is specified relative to PHI20,
the PHI2 clock output of the CPU.
Maybe the delay from PHI0I to PHI1O and PHI2 is mentioned, maybe not...
For instance, the Rockwell R65C02 datasheet, page 12:
http://archive.6502.org/datasheets/rock ... essors.pdf
;---
Now to take a look at a W65C02 datasheet from WDC, year 2000, page 25:
http://archive.6502.org/datasheets/wdc_ ... r_2000.pdf
In this datasheet, the bus timing is relative to "PHI0I", the
clock input of the CPU,
which
went renamed to PHI2 by WDC somehow...
BTW: the datasheet from 2000 says max. 22ns propagation delay from clock input to clock outputs,
in the W65C02S datasheet from 2013 this little remark about the delay is missing on page 26.
http://archive.6502.org/datasheets/wdc_ ... 7_2013.pdf
At 20MHz, 22ns would be nearly half a clock cycle.
;---
Conclusion:
For non_WDC CPUs, use the PHI2O output.
For WDC CPUs, you better stick with the clock input to avoid trouble.
Depending on the chip manufacturer, "PHI2" ain't always 'PHI2'.
.
