You could even eliminate everything except the ROM decoding and a simple output register on the CPLD. Use a single output pin (maybe the QUARTs chip select, with the IC removed?) as an output and attach the logic analyser to it. I assume it is possible to run up the '816 RAM-less? Code in the ROM could then flip the output on and off.

My boards always include a LED on an PLD output pin for this kind of reason.

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No logic analyzer, just a scope and a logic probe. Usually I solve these problems with just the probe. Single-stepping the clock will be a big help. I'm going to build a little gadget for the purpose.


It is possible. In fact, the beginning of the reset handler makes no references to RAM. The ROM I'll use to figure out this problem will consist of two instructions: NOP and STP, neither of which requires any memory access other than the MPU fetching the opcodes from ROM.


Unfortunately, every one of the 32 I/O pins on the ATF1504AS has been allocated to a circuit function.

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I got my little clock single-stepper built and tried it out. Right off the bat I could see where the Ø2 clock might be an issue.

Recall that Ø2 is the output of a flip-flop driven by an oscillator. The single-stepper does nothing more than imitate the low/high output of the oscillator, pulling the flop's CLK input low when a push button is pressed and then bringing CLK high shortly after the push button is released—a DS1813 reset generator debounces the push button. Each time CLK goes high the flop's Q output, which is from where Ø2 is derived, should change state. So, the theory goes, two push button press/release cycles would produce one complete Ø2 cycle, which would allow me to look at various logic levels with Ø2 held in either state.

For initial testing purposes, I put my logic probe on the flop's Q output just to prove that my stepper was stepping. Several times I noted that the probe didn't always say Q was high when it should have been. First thought was perhaps the flop was defective. Then it occurred to me to switch the logic probe (a BK Precision DP-21) from CMOS to TTL mode, which has the effect of changing the probe's notion of what voltage level constitutes a logic 0 or logic 1. Now the probe consistently indicated when Q was low or high.

The logical progression with this would be to replace the 74ABT74 flop with a 74AC74 equivalent, since the latter's outputs when high are very close to Vcc. I don't have any 'AC74s in SOIC14 so I had to order one. That will be the easy part. Replacing it...well, I still can't see from my left eye...

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I tried out the clock stepper on POC V1.1, whose Ø2 clock is derived from a 74AC74 flop. The logic probe, set for CMOS mode, indicates that Ø2 positively changes state with each press of the push button. It looks as though the 74ABT74 flop on POC V2 is going to have to be replaced with the 74AC equivalent.

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I would try to put a strong pull-up first in PHI2, eg something like 330 Ohms.

Tried that, but it made for a poor waveform and had no apparent effect. The flop needs to be changed out with an 'AC74.

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What clock speed did you use with the pullup? That can't be that the waveform is bad. In my opinion there is some sort of connection to PHI2 that should not be.

The input to the flop is 2 MHz, so Ø2 is 1 MHz. The presence of the pull-up makes the waveform somewhat trapeziodal. Without the resistor, the waveform is pretty square.

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Strange. Why should the pull-up make the pulse trapeziodal? There is no reason for that. The ABT output can sink 20mA and source -15mA. The pull-up should virtually have no impact. Certainly not when you stay below the source capabilities. What value did you use for the pull-up.

I used 680 ohms. The 74ABT74 can source 32mA and sink 64mA. It could be the particular flop I used has a problem.

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680 ohms times even 20pF on the line makes for a time constant of 13.6ns. Although that TC picks up after the 74ABT part gets its output as high as it can, it might still be a problem. The specified maximum acceptable rise time for the '816 is 5ns.

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Is this 5ns really the limiting factor here? I doubt. It still puzzles me that the signal is trapezoidal. With 1 MHz each Phase is 500ns. To be able to see a trapezoidal signal with a 680Ohm pull-up is not normal. Even if the RC time of PHI2 due to capacitance is 20ns then you barely can see that. Also the ABT should bring the signal to a reasonable Level in a very short time, less than 3ns. If after the level from the ABT the rest of the edge shows a slow rise time then I still think there is some unexpected load on PHI2. A decoupling capacitor, output, etc.

BDD, how many input signals are connected to PHI2 and what is the rise time of your trapezoidal waveform and is Voh with the pull-up at the expected Level, i.e. 5V?

Not sure what you mean by "how many input signals" but Ø2 (the flop's Q output) drives the '816 and the CPLD. I have verified that there are no other connections to Ø2.

The clock oscillator only drives the CLK input of the flop. Incidentally, I mistyped earlier. The test frequency was an 8 MHz oscillator, resulting in a 4 MHz Ø2.

As for the waveform, I can't explain it but believe at this point that the flop has a problem. It will get changed out and replaced with a 74AC74.

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Indeed the CPU and the CPLD only is not many. I thought there were also some 6522. I agree the flop is now the suspect.

What does the scope say about the GND and VCC pins of that flipflop when its output is misbehaving (ie, pullup attached)? Worth checking, if you haven't already.

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