Yes the instruction is allowed to finish. For anyone who's curious about the exact details of interrupt handling...
Step 1: when the SYNC signal is high (or when the 816's VPA and VDA are both high) it means a new instruction is beginning. Via PC, the CPU fetches an opcode. Typically the opcode is accepted; but this cycle is the timeslot when an interrupt can commence (assuming one has been requested). If an interrupt commences then the just-fetched opcode is discarded. It gets preempted by an internal instruction that resembles BRK. The next step will be 2b, not 2a.
Step 2a (normal): if there's no interrupt then PC is incremented, and in cyle 2 (the cycle following SYNC) the byte at opcode_address + 1 is fetched. The byte at opcode_address + 2 may also be fetched, and other memory accesses may occur, such as to zero-page, stack or general data memory. In other words the instruction is allowed to complete -- after which PC will point to the opcode of the subsequent instruction, and it's time to go to step 1 again.
Step 2b (interrupt): if, during step 1, an interrupt commences, PC is not incremented, which is important. And in cycle 2 the opcode is fetched again and discarded again, which is generally meaningless. Then the thing resembling BRK causes PC -- still pointing at the preempted opcode -- to be pushed. Finally the interrupt vector is fetched, and the thing resembling BRK is complete. PC will point to the first opcode of the ISR, and it's time to go to step 1 again.
At the conclusion of an ISR, RTI pops the return address into PC. When the RTI has completed PC will point to the preempted instruction and it's time to go to step 1 again.
![Question :?:](./images/smilies/icon_question.gif)
Did I hear somebody ask what's the difference between "the thing resembling BRK" and an
actual BRK? Actual BRK sets the BRK bit in the P byte pushed to stack. Also, actual BRK is a two-byte instruction that causes PC to increment by two before it gets pushed to stack.
(ABORT, as Garth noted, causes the currently executing instruction to have no effect. In that regard it does not wait for an instruction boundary. Then when the boundary does arrive -- when the instruction
has "completed" -- the address of the aborted instruction's opcode is pushed, which means when an RTI occurs later it will take you back.)
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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
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