Joined: Fri Aug 30, 2002 1:09 am
Posts: 8545
Location: Southern California
|
Do like a spider web, starting with a star with everything hooked directly into the center which has good bypassing, then connect the ICs around the center to each other.
Attachment:
spiderweb.jpg [ 43.58 KiB | Viewed 1016 times ]
With CMOS which takes very little power, wire resistance is not the enemy. The enemy is inductance, and the main way to minimize it, if you don't have a true ground plane (and no, copper pours and fills don't qualify, nor does nearby sheet metal that's grounded at one point), is to minimize the wire length. The wire size is not as important. 30AWG wire-wrap wire has 27nH of inductance per inch, and going up to 24AWG (twice the diameter, four times the cross-sectional area) only cuts it to 23nH, so not much difference!
In WW boards, you can put the decoupling cap.s under the ICs. Minimize the lead length.
Doing this, you won't have any trouble. See also our sticky topic, "Techniques for reliable high-speed digital circuits."
_________________ http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?
|
|
Login
Register
FAQ
Search
