Understanding the SID

[BigEd]

fastgear wrote:

... an interview with Bob Yannes on the design of the SID
http://sid.kubarth.com/articles/intervi ... annes.html

That's a great find!

[drfiemost]

ttlworks wrote:

BTW: where does the signal RESET come from ?

It comes from outside the chip, this is the description from the reference guide:

Quote:

RES (Pin 5)
This TTL-level input is the reset control for SID. When brought low for at least ten ø2 cycles, all internal registers are reset to zero and the audio output is silenced. This pin is normally connected to the reset line of the microprocessor or a power-on-clear circuit.

While checking the schematics again I noticed that some of the Phi2 and Reset signals are wrong, need to update the graphs, maybe they'll make more sense then.

[fastgear]

Drfiemost, don't know if I am jumping ahead with your planned set of posts with this question.

I have been reading a bit on Fibonacci LFSRs I see it needs an initial non-zero seed value.

What is the seed value that the noise generator use?

[drfiemost]

fastgear wrote:

Drfiemost, don't know if I am jumping ahead with your planned set of posts with this question.

I have been reading a bit on Fibonacci LFSRs I see it needs an initial non-zero seed value.

What is the seed value that the noise generator use?

Yes, that's a topic I'd like to examine soon. As far as I know there is no seed, but a 1 is injected into the XOR feedback mechanism and in some way all the bits end up high.

drfiemost wrote:

While checking the schematics again I noticed that some of the Phi2 and Reset signals are wrong, need to update the graphs, maybe they'll make more sense then.

Ah, (almost) got it! The /Reset line is actually tied to the reset pin while the one marked as Reset comes from the clock instead. There is a complex circuit attached to the Phi2 pin that generates two outputs, I guess it's some sort of clock divider.

[BigEd]

There's a good chance it's generator of two non-overlapping clocks: look for cross-coupled NOR gates which prevent both clocks being high at once.

[drfiemost]

BigEd wrote:

There's a good chance it's generator of two non-overlapping clocks: look for cross-coupled NOR gates which prevent both clocks being high at once.

Yes, I can see the NOR gates, but there are some other things that baffle me, will post more on this later.

Meanwhile here comes the reset input. There's a ggNMOS for electrostatic discharge protection, then a push-pull inverter and, after a clocked gate, a couple of inverters. Not sure what this does, I'd say it regenerates and inverts the signal (the input is active low).

[drfiemost]

Here is the first attempt at reconstructing the clock circuitry. The transistor size is not represented in the schematic.

There are two symmetrical parts that produce two signals used to clock the digital logic of the chip, sid_clk2 which is high when phi2 is high and sid_clk1 which is high when phi2 is low. There are also some timing effects involved, as bigger transistors have longer switching times, but I don't think these are critical for the analysis so I won't get a headache over this for now. The one thing that instead puzzles me is why there are two inverters powered with Vdd at 12V while the remaining are connected to Vcc at 5V...

There are also two other lines driven by push-pull inverters that forward the inverted phi2 signal to the R/W and CS pins circuit and to another part of the chip which I haven't looked at yet.

Edit: updated transistor schematic
Edit2: fixed transistor schematic again

[BigEd]

OK, so we do see the cross-coupled NORs to make non-overlapping clocks.

Looks to me from the layout - but not the schematic - that sid_clkX have both pulldowns and pullups, as you'd expect. Big transistors too, which again you'd expect for a global clock.

If there's a 12V VDD rail, it could be to help with the analogue circuitry. Or it could be an elevated rail to help drive critical signals like clocks hard - getting fast full-rail rising edges is hard in NMOS, even with depletion loads.

[ttlworks]

Problem:
For better understanding and trying to re_draw the circuitry,
it would be better to know which transistors are P transistors and which transistors are N transistors,
in other words: which switches are normally closed and which switches are normally open.

[BigEd]

Hang on, it's NMOS, not CMOS - depletion transistors are not inverse sense the way PMOS ones are. (It's an easy mistake - I've done it myself.) Edit: the normal enhancement mode transistor is normally off, and conducts when the gate voltage rises. The depletion mode is normally just about on, and conducts even more when the gate voltage rises. You could only turn it off by bringing the gate negative, which doesn't normally happen.

That said, there is a notation for depletion-mode: an extra bar across the channel. See fig 2b on page 6 of
http://ai.eecs.umich.edu/people/conway/ ... V1.Ch1.pdf

(All the symbols on the wikipedia page are unnecessarily cluttered - don't use them!)

Edit: even without a special symbol, you can see the depletion mode as they always have the gate tied off to the source. (Or drain, I'm never sure)

Edit: but I would say always draw power at the top and ground at the bottom, similarly to always trying to get signal flow from left to right - stay too close to the layout and the schematic is very hard to understand.

[BigEd]

(The simplest model for the depletion mode transistors is that they act as resistors - that's a good enough model for almost all purposes. Any transistor hanging off the power rail with gate connected to source acts logically like a pullup resistor.)

[ttlworks]

The reason why I'm asking about "normally open" and "normally closed" switches is,
that the results of my reverse_engineering attempts don't make sense to me so far.

For instance, when trying my luck with the SID_CLKx circuitry...

I assume, that this part of the circuitry is for delaying the falling edge of a signal:

sid_clk1.png (11.07 KiB) Viewed 9366 times

Edit: deleted two schematics because they were plain wrong.

[BigEd]

That circuit you're thinking of as a delay is called a superbuffer - usually used to drive a large capacitance, because it has better rising edge drive than a conventional buffer. Although, if it isn't driving a large load, perhaps it is there for delay??

I see four inversions after the NOR gates, two of them before taking off the clock signals and two of them after. So, logically, that's just the same as the NOR gates alone, which means the two signals will never both be high. That sounds right. Now we have to add back in the delays... and I don't know what we get.

It's also possible that the schematic as drawn isn't right!

[ttlworks]

We better assume, that some of the signal names\labels on the silicon are not too correct,
and maybe the transistor level schematics contain the one or other little bug...
this would explain quite a few things.

Also, my propagation delays in the picture above are not to scale
and most certainly wrong.

;---

NMOS 6502 clock generation schematic, Beregnyei Balazs:
http://www.visual6502.org/wiki/index.ph ... _documents

Unfortunately, it's too different from the SID_CLKx logic above to be really useful now,
but when drawing transistor level schematics of the silicon,
drawing transistors in the schematics at a size which corresponds to the size
of the transistor on the silicon suddenly is starting to make sense to me...

[drfiemost]

ttlworks wrote:

And when I'm trying to re_draw the whole circuitry, I'm getting this:

sid_clk3.png

SID_CLK1 and SID_CLK2 are supposed to be non_overlapping,
so something most certainly went wrong during reverse_engineering.

Surely I may have made some mistakes, in fact it looks like the 12V inverters are actually push-pull inverters, need to double-check the schematic again.
However there are no inverters on the SID_CLKx output lines and if you invert the signals on your clock graph those won't overlap, so it seems we're on the right track