Simple 65C816 SBC with 512K?

[cbmeeks]

My searching skills have failed me. Does anyone have schematics for a simple SBC that uses a 65C816 and 512K of SRAM?

Doesn't have to be exactly 512K. Just anything more than 64K...but not anything super large like 4MB.

I've got some 128K and 512K SRAM chips gathering dust.

Oh, I'm familiar with the memory decoder that's for sale. But I'm looking for something I can build with the parts I have.

Thanks!

[cbscpe]

Are GALs or CPLDs something you have or do you require an all HCT design? And what is your goal regarding the clock rate?

[cbmeeks]

Well, it's funny you ask that.

Normally, I would say all discrete parts because that's what I have and I'd like my designs to be in "kit form" for other beginners like me.

However, I *do* have one FPGA dev board that I thought about prototyping with it and then perhaps convert to a CPLD or GAL.

I was going to ask in a separate question about using GALs or CPLDs in this "FPGA world". So to answer your question, discrete logic would be nice if it weren't too overwhelming.

But, if a through-hole PLD device could handle all memory mapping, I would be up for that as well. My only turn-off for the PLD was that I seem to always be redirected to FPGA when I research. FPGA is hard to design for (for me, anyway).

On the clock rate, I was thinking anything between 2-8 MHz. I know when you start approaching 8-10MHz, the designs get much more complicated. So anything that leans more towards easy (slower) than fast (harder) would be fine.

[cbscpe]

Its just because I was in a similar situation. First my designs started with descrete logic and the systems were limited to simple designs and to an address space of 64kbyte. Then I started to use GALs. This allowed me to put all the GLUE into one or two GALs. Still limited to 64kbyte but speed increased to 12MHz and allowed for more options (see my ROMulus 1st). When I was starting to increase RAM I soon found that a system using GALs is possible but for a decent complexity I ended with designs having four or more GALs and speed was limited to 5MHz. So thats when I started with CPLDs. I don't want to use FPGA for the same reasons you mentioned and because the designs would no longer run with 5V. The biggest limitation of CPLDs is the number of IO pins. You need to take into account the number of address bits you want to decode and the granularity. But a 32 IO pin CPLD should be sufficient when you limit yourself to 19 address pins.
For a more detailed discussion it would be helpfull to know the features your system should support. E.g. how many chip selects you need, whether you want to support slow ROMs (dynamic dual clock rate) or any bootstrap method discussed in other posts or if you want to overlay the ROM with RAM after the bootstrap.

[cbmeeks]

Thanks for the great response.

Well, I haven't spec'd anything out yet. Everything is in my rat's nest of a brain. lol

I enjoy playing around with Propeller micro-controllers for audio and video. But they aren't fast enough for large memory glue logic. My ideal "second generation" computer would drive audio/video (VGA) and 512K of RAM (plus a few I/O devices, etc.).

I only mention 65C816 because everyone keeps saying it's easier for larger RAM requirements. I'd be happy with 65C02 but I imagine the bank switching is more difficult. Like the soft-switches of the Apple IIe.

Anyway, what CPLD's would you recommend? I also don't care about 5v. 3v3 is fine with me. DIP packaging would be nice, however.

Also, how do you program the CPLD's? I've only programmed one FPGA chip and various micro-controllers. But they all had onboard Atmel designs to translate from USB to whatever.

Finally, where can I go to learn more about CPLD and memory decoding. Every time I search I seem to find nothing but FPGA and SDRAM which I'm not interested in.

Thanks!

[BigEd]

Daryl's SBC-3 might be worth a look:
http://sbc.rictor.org/sbc31/info.html

It uses a big CPLD to connect a 512k SRAM to an '816. It might be that most of the CPLD is to provide video output, rather than bank-switching glue.

[cbmeeks]

Cool! Thanks for the link.

[BigDumbDinosaur]

cbmeeks wrote:

My searching skills have failed me. Does anyone have schematics for a simple SBC that uses a 65C816 and 512K of SRAM?

Doesn't have to be exactly 512K. Just anything more than 64K...but not anything super large like 4MB.

I've got some 128K and 512K SRAM chips gathering dust.

Oh, I'm familiar with the memory decoder that's for sale. But I'm looking for something I can build with the parts I have.

Thanks!

Lattice 22V10 GALs, rated at 10 or 15 ns, are still available through some sources. You only need three high address lines to control a 512KB RAM. So your GAL would generate A16, A17 and A18. It's possible with discrete logic (74AC or faster) but having the bank latching in one place makes life easier.

[cbscpe]

A GAL is not suited to latch the bank address as it is edge triggered and you loose the part of the address ready time during PHI2 is low. A transparent latch as in the recommendation from WDC is preferable for fast systems. Only for a 74ACT573 you need the inverted clock. But then you end up with multiple ICs. I think a small CPLD with 64 macrocells is the smplest solution and can implement alll the GLUE logic for a system with 512kbyte RAM. Using a through hole PLCC socket makes them reasonably usable for standard prototype PCB. An ATF1504 can easily do that. For a complete system CPU, SRAM, CPLD, VIA, USART is all you need,except for the boot code. Here I would recommend a bootloader using an AVR or PIC. The microcontroller can also provide the clock and the reset for the system. A total of six ICs is all you need then.

[Dr Jefyll]

cbscpe wrote:

A transparent latch as in the recommendation from WDC is preferable for fast systems.

Good point, Peter.

In a case like this it's worth remembering that an ordinary tri-state buffer such as 74_244 -- or some GAL IO pins acting as a '244 -- can be used as a transparent latch if certain conditions are met.

• all devices driven by the "latch" must have high impedance inputs (typical of 74HC and 74HCT devices and of NMOS and CMOS logic and memories).
• no DC loads (pullups, LEDs, 74LS devices) can be driven
• the duration of the inhibit state must be limited to a few microseconds

When the outputs of the buffer inhibit ("float" or go tri-state), capacitance will temporarily keep them and the connected inputs in whatever state they are in (high or low).

BigDumbDinosaur wrote:

Lattice 22V10 GALs, rated at 10 or 15 ns, are still available through some sources.

Yes, even though the Lattice product is discontinued. The Atmel ATF22V10C is presently carried by Mouser. This is a 5 volt device boasting a 5 ns maximum pin-to-pin delay.

This Atmel part also features "I/O Pin-keeper" circuits which make it exempt to the third condition noted above. Ie: data will remain valid indefinitely even after the buffer inhibits.

Using their tri-state buffers as transparent latches, either the Lattice or Atmel GALs could be used to implement the "glue" in an '816 SBC.

-- Jeff

Atmel ATF22V10C.pdf

(1.78 MiB) Downloaded 103 times

I-O pin-keeper.png (10.19 KiB) Viewed 1902 times