I've read that the Apple 2 does DMA by actually halting the clock signal, which is one reason I was thinking that DMA might not be an intended use.
Stopping the clock is only practical with the WDC version of the 65C02, and 65C816, both of which have fully static cores. Stopping the clock with any of the NMOS MPU's will cause loss of register content—there's a minimum clock frequency at which the NMOS parts must be run to assure reliability.
If you design something new it should be with the WDC 'C02 or '816, not the NMOS parts. Aside from the clock matter, the CMOS parts fixed errata in the 6502, and added new instructions and new addressing modes for existing instructions. Last but not least, the 'C02 and '816 can run at much higher clock rates.
Now that I think about it, I recall someone (somewhere online) mentioned the possibility of it being to enhance the integrity of RMW operations, so that when applied to peripheral devices the new value is written shortly after the value it was based on... inserting large amounts of time between the read and write might have odd consequences.
R-M-W operations on I/O hardware are in that category of things that are frowned upon in the world of professional software development. In executing a R-M-W instruction, the 6502 will do a "dummy" write on the target register before writing the final value, which could result in some strange device behavior. The 65C02 is more benign in that regard, doing a dummy read before the final write. The 65C816 has additional outputs to tell glue logic when access should be allowed.
Might it also provide atomicity (atomicness? LOL) for locks in a multi-processor bus? At least on the NMOS version I think this would be a benefit, since a (dummy) write cycle begins immediately after the read. But on later versions this benefit probably disappears.
At the time of its development, the 6502, being a low cost alternative to the then-current Intel, Motorola and Zilog offerings, was not a candidate for a multi-processor system. When the Commodore VIC-20 was introduced in 1980, it effectively had a multi-processor design, as the VIC (
Video
Interface
Controller) used the same buses as did the 6502 to fetch data from video RAM. As the 6502 has no specific control inputs that would allow another device to claim the buses (no BE input, as is present on the 'C02 and '816), Commodore had to use external silicon to get the two devices to cooperate. The C-64 and C-128 also had this issue.
The WDC 65C02 and the 65C816 have an output—MLB—specifically intended to address bus contention issues during R-M-W instructions. MLB is normally high, but goes low during the cycle in which the MPU writes out the final value to the location being modified. That tells other potential bus masters that they must not attempt to claim the bus.
