Hello all. Been a while since I've been on here.

I'm toying with some ideas for a computer I'm building. SRAM is pretty cheap (for hobbyists, anyway). I have a 512K SRAM module that I want to map to a 6502.

I will also be using a Parallax Propeller MCU for glue logic, video, etc.

I've never built anything with bank switching. But, I would go insane knowing that my 512K was sitting empty and only using 64K.

It seems to me that PAGE 0 should also be static and never move. That way, PAGE 0 values would always be the same no matter what bank you're in. Also, I'd like 1-2K of static RAM to never move after PAGE 0 for system values like background colors, char locations, etc.

So, I have no idea where to start on this. My simplistic mind is thinking of doing something kinda like the Apple II.

Maybe have a reserved location that contains a byte. That byte would contain the 8 MSB bits starting at A18. Which would give me 8 banks of 64K. I guess I would need to XOR the 8 pins or something.

Anyway, any ideas or websites where I can learn how to do this would be great.

Thanks for any help!

_________________
Cat; the other white meat.

Have a read through the Bank Switching Scheme Debate topic.

The 65816 handles all the problems of banks far more gracefully than the '02 can, and offers a ton of other benefits anyway, so I don't think there's any point in trying to do bank switching on a 6502. (I don't deny that it's an interesting subject though.) If you do it though, I would point out that extending page 0 (or any part of the map, for that matter) into all banks will make it more impractical to have large data arrays that cross bank boundaries. Data is the primary reason to have all the extra memory on a 6502, particularly as it's not well suited for multitasking, so you almost certainly will never fill a whole bank with actual program code on a 6502. It would probably be at least as practical to have a section of, say, 8KB in the 6502's 64KB address space to be a window into the larger address space.

512KB module? You can get singe 512KB 5V SRAM ICs, even in DIP, and in fact the 4-megabyte module I offer use eight of these (although I use the SOJ package), four on each side. There's a picture on the front page of my website linked below, and the link to the data sheet is there too.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Well, that may be true. But, it seems the 65816 isn't the easiest item to obtain.

Besides, the 6502 is my favorite CPU and my retro computer is going to be based around it. Well, the 65C02 anyway.



Ah, that's a good point. I didn't think of that.



Well, there's also the point of what I have on-hand.

At the time I purchased some 512K units, I was looking for 128K units but the 512's were just a little bit more so I thought what the heck.

_________________
Cat; the other white meat.

I take it then that you're not in the U.S.. The '816 is in current production, and is stocked and available any day of the week from multiple distributors.


You can initially use the '816 exactly as if it were an '02, and then bring in the extra capabilities later, little by little, as you are comfortable.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

No, I'm in the US. I could only find them on Mouser (which I use all the time anyway) but I thought I saw that none were in stock. Something like 98 were "on order". That's for through-hole, anyway.

And the SMD version only had like 30-something in stock. So I just took it as a device that isn't in high demand (and perhaps, near EOL).

I'd love to be wrong about this, BTW.

The idea of using a "6502 with 24bit address bus" does sound appealing.

If I went that route, I'd want to use a microcontroller (if possible) to do address decoding and not use a CPLD or anything like that. Trying to keep it as hobbyist friendly as possible.

So, any tips on using the '816 and a microcontroller to address 512k RAM?

Also, I'm thinking it might be more helpful if I explained a little more on what I want to use the memory for.

I'd be happy with restricting 64K for code execution and the rest as bankable buffers for things like graphics, char sets, audio, etc.

Thanks!

_________________
Cat; the other white meat.

Hmmm... It looks like the list of distributors for it in the U.S. is shorter than I remembered, and Jameco does not have the '816. You can always buy directly from WDC itself though. They clearly have no intention to ever quit making it, even though the sales volume of the off-the-shelf version is very low.

I think you'll find that a microcontroller is not fast enough to replace glue logic—although I remember there are some PICs that have a minor amount of logic that can be configured in the PIC code when it runs. However, having so many address bits (24) might be an advantage to simplify address decoding if RAM will only take 1/32nd of the 16MB map.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

The microcontroller I'm using is the Propeller running at 25MIPS per core. My CPU speed will be within 1.79 MHz and 3.59 MHz.

The naive engineer in me thinks that wrangling the MSB of A18:A16 should be easy but I just can't wrap my head around it. Lol

_________________
Cat; the other white meat.

25 MIPS is 40ns per instruction, and it will take a few instructions to read the address bus, do one or more logic operations (or perhaps it would be a look-up table), then send the result to an output port to select the right device. For a 14MHz '02, the tADS address setup time is 30ns max, out of the 280ns of phase-2-low time that you get at 1.79MHz, leaving 250ns min. A 14MHz 65c22 VIA needs 10ns tACR setup time for register selects and R/W\, leaving 240ns. That's approximately six instructions of the microcontroller, depending on when it grabs the address to read and how long the output takes to reach the pins. That might work, if the µC runs this in a tight loop and has no branching other than to get back to the beginning of the loop, and does not use interrupts, and the beginning of the loops starts executing 30 or 40ns after the fall of phase 2.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

The Propeller running at 100 MHz has 4 clocks per instruction so you get 25MIPS at 10ns per instruction IIRC.

And I'm not using a 6522.

_________________
Cat; the other white meat.

Wait. You're right. It's 40ns.

However, there is a way using counters to achieve 12.5 ns per instruction at 80 MHz. I can't remember how but I know I've read it several times.

I will have to look into that again.

_________________
Cat; the other white meat.

Both forms of the 65C816 are current production. Mouser's stock ebbs and flows, and at the end of the year, tends to ebb in order to reduce the inventory value for tax purposes.


I don't think you'd be terribly impressed with the performance of such a combination. It can be done entirely with discrete logic, but is really a job for a CPLD. CPLDs exist for a reason, and that is to create elaborate glue logic without incurring significant performance penalties. Microcontrollers are not particularly well-suited to bare metal glue logic functions and tend to handle them relatively slowly. You should pick the proper tools for the job.


If you use the 65C816 as it is intended to be used with one of Garth's DIMMS, you'd have 4MB of RAM, with contiguous addressing spanning from $010000 to $3FFFFF, which is 3.93MB. That would be lots of room for your planned data structures.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

Well, 90% of my data structures would be for audio/video work. Which the microcontrollers need.

I just hate having so much RAM sitting there empty.

CPLD isn't really an option at the moment. I am *slowly* learning FPGA and have one FPGA dev board but FPGA is hard and not very hobbyist friendly. I'd like my final design to be easy to assemble on a breadboard.

Much like the Propeddle project.

So, how did the Apple II use 128K or more without CPLD/ASIC chips? I guess I need to get those schematics back out and see what they did.

_________________
Cat; the other white meat.

Have you given up on the '816, then? The Apple II design would certainly have included the '816 if it were available at the time. It is the easiest path to expanding the amount of memory.

BTW, discrete logic (74__ series chips) takes more space and is somewhat slower but is still a viable substitute for CPLD. That applies whether you use the '816 or attempt your own address expansion scheme.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

No, I haven't really given up on anything. I'm just researching and learning a ton.

The '816 is certainly starting to look better. I'm a little put off (however) that it is harder to get. I hope that is the end-of-year inventory scenario mentioned earlier.

My first love (hardware wise) was the 6502. So the '816 still fits that mold. Meaning it's not out of the equation.

Anyway, like I said, I am limited to what I have on hand.

I plan on spending the rest of my life learning and building various circuits so it's all good.

I just don't want to delay my first SBC because I'm messing around with some CPLD software package or development board. I want to use off the shelf components that are breadboard friendly at first.

But again, to have a 512K SRAM module and only using 64K of it would drive me insane. LOL

Thanks.

_________________
Cat; the other white meat.

That doesn't make any sense to me. The 65C816 is a phone call or mouse-click away, same as any other item that Mouser et al stocks.


Think of the '816 as a 65C02 on steroids. All of the "traditional" instructions are there, plus new ones to make life easier for the assembly language programmer.


So build it with discretes, as Jeff suggested. The only real downside to building with discrete logic is space usage.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!