CMOS Inputs and Floating Bus Questions

[ndru]

1. Since the 6502 data bus floats for about half of every clock cycle, isn't this dangerous to CMOS inputs (memory, latches etc.) connected to it? Are pull-up/pull-down resistors necessary in this case?

2. Do any normal (LS/HC/HCT etc.) chips have the Bus-Hold feature that seems to be exclusive to the 74ALVCH series?

[kc5tja]

ndru wrote:

1. Since the 6502 data bus floats for about half of every clock cycle, isn't this dangerous to CMOS inputs (memory, latches etc.) connected to it? Are pull-up/pull-down resistors necessary in this case?

The 6502 never floats its buses. Indeed, this is one of the reasons why Commodore didn't use the 6502, but an enhanced version called the 6510, in the Commodore 64. To do any kind of DMA with 6502, you would need to negate the RDY signal, wait some four clock cycles to ensure that any writes complete, then disable any external bus transceivers or buffers, so that other devices can have the bus.

Quote:

2. Do any normal (LS/HC/HCT etc.) chips have the Bus-Hold feature that seems to be exclusive to the 74ALVCH series?

What is this bus hold feature? And what specific parts are you referring to that have this feature?

[GARTHWILSON]

> The 6502 never floats its buses.

Actually, the data books do say the data bus outputs are three-state buffers. (The address bus outputs are not three-state except on WDC's, which have the bus-enable input pin.) It's not a problem though. As recently discussed in http://www.6502.org/forum/viewtopic.php?t=642 , bus capacitance holds data far longer than you need when there's no longer anything driving the bus, assuming all loads are CMOS.

CMOS inputs have very high gain, and the only risk with having very slow rise times is that a gate whose output is driving something can oscillate as the input slowly crosses the logic threshold. There's no risk of current becoming excessive and the part getting hot. In fact, Fairchild (and probably other manufacturers) have ap. notes on using digital logic (mainly inverters) in an analog mode. However, a memory that is not selected is not driving a load; and as long as R/W\ is high, its data will not be corrupted either.

WDC's 65c02 does have a BE (bus enable) pin too, allowing you to turn off the address, data, and R/W\ buffers for doing things like DMA with no external buffers or transceivers.

Even with the older 65c02's that don't have the BE pin though, with all CMOS parts you can have the entire computer run on a fraction of a milliamp if you turn the clock speed down low enough. I've done it, using 74HC glue, which does not have the bus-hold feature. I had very weak pull-up resistors on four of the data lines because of a hardware RTC I was using that had open-drain outputs in its 4-bit interface. It was ok for the pull-ups to be very weak because the clock speed was so slow, and the RTC was too slow to directly address at more than 200kHz anyway.

The bus-hold feature BTW Samuel is what WDC's VIAs have one the port pins, that hold them at the last logic state when there is no longer anything driving them. You can see the diagram in their data sheet which shows a couple of series inverters with the input of the first one and the output of the second one tied to the same port line. The output of the second one is extremely weak so it doesn't contribute appreciably to power consumption or heating or make the input difficut to flip or pull up or down passively.

[ndru]

Thanks guys. I found that Texas Instruments actually makes stand-alone bus-hold chips (no DIP package though), namely the SN74ACT1071 and SN74ACT1073.

[GARTHWILSON]

I hope I don't sound abrasive here, but I don't know how else to say it. Unless you're trying to do something really special, I think you're trying to solve a problem that does not exist. Bus-holding is simply not necessary. In most cases, neither is bus-buffering.

[ndru]

I'm actually designing my first ever 6502 project, and trying to get it to work entirely within the timing specifications in the datasheets. I'm probably worrying too much about the 65C02's data hold time being too small (due to propagation delays in the glue logic etc.).