WDC MPU TTL Compatibility

[cbscpe]

The datasheets of WDC are correct. The reason the input levels are this way has nothing to do with failing to adjust the thresholds. It's because the WDC CPU's are specified for a extended voltage range and this can only be achieved by a symmetrical input behaviour. That means for guaranteed operation vih must be 0.8 VDD. Of course in most cases vih even closer to 50% of vdd will be recognized correctly. How close depends on the threshold of the input transistors, and fromthe fact that the WDC chips work at 1.8V this mght be not too close to 50%. But it might take some additional time. I have observed this as well. E.g. some test SBC's did not support the expected PHI2 speed,but with some pull ups on the databus I got closer but not really much.
So the WDC CPU work like an AC logic and not at all like a ACT.
As for the Cypress SRAM, mostly we use the 10ns Version. 10ns is guranteed for a TTL output level. Some ns later it will be well above it. But that is not guranteed, however in many cases this works.
I suspect that best results can be achieved by running the CPU at 0.5-0.7V less than the rest.

[Dr Jefyll]

BigEd wrote:

It looks like their recent (90nm) offerings are running a 3.3V I/O supply even though the chip supply is nominal 5V - would that explain everything?

At least for the questions in my mind, yes, it would explain everything. (Except maybe, "why did they do that?")

Where are you seeing the bit about 3.3V I/O supply, Ed? Both supply pins are labeled simply VCC; no special details. I'm curious to get to the bottom of this.

[GARTHWILSON]

I just measured (on the oscilloscope) the data output voltages from the WM-1 4Mx8 5V SRAM memory module with the CY7C1049D SRAM chips under test and they're putting out 3.8V, well above 70% of Vcc.

However, looking back at the '816 datasheet, the schematic of Figure 5-1 showing the bank latching circuit shows a 74x245 bus transceiver, and that of course can be a 74ACT245 or 74ABT245; so the TTL voltage threshold requirement becomes a non-issue if it is done that way.

Edit: Darn! Scratch that. According to the data book, 74ABT's output, even without a load, does not pull up any higher than the SRAMs do! Is there anything faster than ACT that has TTL input thresholds and yet can pull up virtually all the way to the positive rail on the output?

(With that said, I have not gotten a single complaint about the memory modules I've sold.)

[BigDumbDinosaur]

GARTHWILSON wrote:

I just measured (on the oscilloscope) the data output voltages from the WM-1 4Mx8 5V SRAM memory module with the CY7C1049D SRAM chips under test and they're putting out 3.8V, well above 70% of Vcc.

However, looking back at the '816 datasheet, the schematic of Figure 5-1 showing the bank latching circuit shows a 74x245 bus transceiver, and that of course can be a 74ACT245 or 74ABT245; so the TTL voltage threshold requirement becomes a non-issue if it is done that way.

Edit: Darn! Scratch that. According to the data book, 74ABT's output, even without a load, does not pull up any higher than the SRAMs do! Is there anything faster than ACT that has CMOS input thresholds and yet can pull up virtually all the way to the positive rail on the output?

(With that said, I have not gotten a single complaint about the memory modules I've sold.)

Well, I have a 74ABT541 on my SCSI host adapter to put the state of the 53CF94's DREQ output on the data bus during SCSI I/O. That is, the '541 is directly driving D0-D7, and it works reliably. I'm suspicious of WDC's ViH spec, because going by what they're saying none of this should work.

[Dr Jefyll]

GARTHWILSON wrote:

Is there anything faster than ACT that has CMOS input thresholds and yet can pull up virtually all the way to the positive rail on the output?

That has TTL input thresholds, I think you mean. See if this 74VHCT245 has the speed you want.

Apparently NPX makes one in a SOIC package. This datasheet is for Toshiba, and they only offer TSSOP. Both are in stock at Digikey.

[GARTHWILSON]

Dr Jefyll wrote:

GARTHWILSON wrote:

Is there anything faster than ACT that has CMOS input thresholds and yet can pull up virtually all the way to the positive rail on the output?

That has TTL input thresholds, I think you mean.

Yes, of course-- I'll fix it.

Quote:

See if this 74VHCT245 has the speed you want.

According to my old National Semiconductor data book for 74ACT, the ACT is slightly faster than that.

Quote:

Apparently NPX makes one in a SOIC package. This datasheet is for Toshiba, and they only offer TSSOP. Both are in stock at Digikey.

I don't have any trouble with SOIC, but I'd rather not going the TSSOP route.

[BigEd]

BigDumbDinosaur wrote:

I'm suspicious of WDC's ViH spec, because going by what they're saying none of this should work.

Surely that's not the case BDD. If a design is out of spec, then it's out of spec - that doesn't mean it won't work. It only means that it might not work, under some conditions and with some in-spec parts. In other conditions or with another in-spec part, it might be entirely reliable.

Remember how it works with silicon fabrication: it's a baking process, and batches come out different. There's variation across the wafer, between wafers in a lot, and between lots. Also, if made in different fabs, variation between fabs. It's quite possible that one whole year of production is fine for a particular not-in-spec design, and another year there'll be a week of production which isn't fine. Could be that it doesn't work, could be that it's unreliable.

The nature of this is that you can't draw a conclusion from a working circuit, at least, no conclusion stronger than "this circuit, presently, seems to work."

You can draw a stronger conclusion from a not-working circuit!

(The other factor you have to take into account with specs is that they cover a range of temperatures and voltages. If you're not soak-testing at the extremes of rated temperature and the extremes of rated voltage, you haven't yet determined the behaviour of your circuit, or of your chip.)

In hobbyist land, we just don't need to be so strict. But this is why specs are the way they are, and it's why most parts will, most of the time, behave well inside the specifications.

[jmp(FFFA)]

I think I mentioned earlier that several years ago I did some testing of V(ih) and V(il) levels for some HC parts (logic gates) and found that they invariably switched around 50% of VDD (+/- 10%). This despite the fact that the datasheets say that V(ih) and V(il) are 70% and 30% of VDD respectively. Probably wouldn't be too difficult to wire up the inputs of the SRAM chip to a potentiometer and write a program to read from them and display the result in a loop to see what the real V(ih) and V(il) are.

Perhaps it is true that over the full temperature range these thresholds can deviate as far as the spec says, but unless things have changed in the way these chips are fabricated recently, I expect this explains why BDD is not seeing sort of problems interfacing TTL to CMOS that we might otherwise expect.

I agree with the sentiment that it is a disturbing new trend to see that some newer "5V" CMOS parts only have a V(oh) of 3.3 volts. Sounds like some marketing folks got together with some wayward engineers in order to figure a way to get rid of the "5V tolerant" label and produce these mutant parts that can't decide whether they are running at 3.3 volts or 5 volts.

[BigEd]

Dr Jefyll wrote:

BigEd wrote:

It looks like their recent (90nm) offerings are running a 3.3V I/O supply even though the chip supply is nominal 5V - would that explain everything?

At least for the questions in my mind, yes, it would explain everything. (Except maybe, "why did they do that?")

Where are you seeing the bit about 3.3V I/O supply, Ed? Both supply pins are labeled simply VCC; no special details. I'm curious to get to the bottom of this.

It's a hypothesis - we know that FPGAs use independent core and I/O power supplies, although they do bring them out to pins. We also know that early 80s ULAs had an on-chip low-voltage regulator to run the core at a much lower voltage. The app note you linked says "issues faced when using the new-generation 90-nm Cypress SRAMs" which implies that there has been a change for the 90nm generation. (It's increasingly difficult to make ever-finer silicon processes tolerant of high voltages, which is part of why we've moved down from 5V to 3V3 to 2V5 to 1V8 - it helps power dissipation, but it's actually near-necessary not to punch through the ever-thinner gate oxides.)

Now, I'm not sure how you'd regulate from 5V down to 3V3 on-chip without dissipating lots of heat or using an inductor...

But I thought the illustration in the app note was indicative of a 3V3 output driver:

6502.org wrote:

Image no longer available: http://www.cypress.com/sites/default/files/inline/fckImages/AN6081-11.jpg

Edit: here's a reference for onchip multi-rail power supplies in modern chips.

[Arlet]

When I read the datasheet, the low voltage hypothesis also crossed my mind. Many modern microcontrollers also run with low voltage cores and on-chip regulators. I guess they just use linear regulators, and a clever way to dump the heat.

[BigEd]

Here's a very cunning plan: split the input rail into two by running two memory arrays as a voltage divider. To avoid power dissipation you need to store energy - normally an external inductor but perhaps you can do it with (on-chip) capacitors.

Edit: here's another highly technical treatment. And here's a slightly less technical one.

[Dr Jefyll]

Thanks for the info, fellas. Re the Cypress RAM I'm guessing they had an established 5V product that was still selling well but they knew cost savings could be realized by going to the smaller process -- which, as Ed notes, means lower internal voltage. They couldn't change the pinout of an already-established product, so the existing VCC pins had to be used, with the internal voltage derived via a regulator. Does this seem like a plausible explanation for why the product exists? After all, they could've just made an all-3V part and called it a day!

It'd be possible to run the internals at 3V yet have the I/O circuitry run at 5v -- some chips do that -- but I guess they concluded most of their customers wouldn't benefit from 5V output, given that TTL input levels are still widely acceptable (although perhaps less so than in the past).

BTW re heat dissipation, the heat added by the on-chip regulator would be offset somewhat by reduced dissipation in the RAM itself. And part of that has to do with driving the bus capacitance. Charging and discharging the data bus capacitance to 3V takes less energy than doing so to 5V.

-- Jeff

[GARTHWILSON]

jmp(FFFA) wrote:

I think I mentioned earlier that several years ago I did some testing of V(ih) and V(il) levels for some HC parts (logic gates) and found that they invariably switched around 50% of VDD (+/- 10%). This despite the fact that the datasheets say that V(ih) and V(il) are 70% and 30% of VDD respectively. Probably wouldn't be too difficult to wire up the inputs of the SRAM chip to a potentiometer and write a program to read from them and display the result in a loop to see what the real V(ih) and V(il) are.

CMOS gates tend to have a pretty high gain, so there's almost no "no-man's land" around the threshold voltage (which is usually half Vcc). However, there's the problem that the propagation delay through the gate will be much higher if the input goes only a little way into the opposite logic level. IOW, getting the specified speed performance will require getting the input more than just a little way into the logic "1" area. I suspect that's where the 70%-of-Vcc spec comes from. It's not that 52% doesn't qualify as a "1", but that you have to get to 70% for the speed guarantee to be valid.

[jmp(FFFA)]

Arlet wrote:

When I read the datasheet, the low voltage hypothesis also crossed my mind. Many modern microcontrollers also run with low voltage cores and on-chip regulators. I guess they just use linear regulators, and a clever way to dump the heat.

FWIW, this is what Microchip does with all of their 32-bit offerings, as well as their newer 16-bit and 8-bit offerings. Most of them (3.3 volt or 5 volt parts) run at 1.8 volts internally.

A typical 16-bit MCU might use around 0.5 mA/MHz and be clockable up to around 70 MHz. So that's a worst case of about 35 mA at 5 volts. If it's running internally at 1.8 volts, that's 112 mW of additional power dissipation it may need to dissipate in package as small as a DIP-14. Consider, for example, that a LM386N-4 (in a DIP-8 package) is rated at 1 watt of power dissipation, it doesn't seem like it's going to be much of a problem to get rid of the extra heat.

[jmp(FFFA)]

GARTHWILSON wrote:

CMOS gates tend to have a pretty high gain, so there's almost no "no-man's land" around the threshold voltage (which is usually half Vcc). However, there's the problem that the propagation delay through the gate will be much higher if the input goes only a little way into the opposite logic level. IOW, getting the specified speed performance will require getting the input more than just a little way into the logic "1" area. I suspect that's where the 70%-of-Vcc spec comes from. It's not that 52% doesn't qualify as a "1", but that you have to get to 70% for the speed guarantee to be valid.

My testing wasn't very comprehensive, but it did involve taking a 1 MHz square wave, applying it to the input of a gate under test via a potentiometer, and examining the gate output for the point at which it stopped outputting the square wave reliably. I'm sure you're right that in order to get the rated speed out of the part, you'd need to stay closer to the 0.3 and 0.7 thresholds. But when we use a part that's good for 15 MHz at 1 MHz, perhaps those thresholds are a lot closer to 0.5 as you suggest and as I've observed in the past.

I am tempted to try the experiment again and factor the frequency of the square wave into the results as well.