http://archive.6502.org/datasheets/mos_ ... v_1985.pdf

Page 5.
NMOS 6502 :
- minimum clock frequency 50 kHz.
- cycle time (for 1 MHz) min Tcyc 1000 ns , max not defined.
- PWH0 max 520 ns

And now 6512
PWH01 :min 430 ns , max not def.
PWH02 :min 470 ns, max not def.

and now the questions:
1. Does this mean that I can stop the clock in 6512 in each cycle and in 6502 only in the phase of L?
2. If not, what will be the effect of the freeze clock in 6502?
Is threatens to damage?

There's no danger of damage - incorrect operation is the risk when running the clock too slow. I don't believe an NMOS 6512 can really stop the clock in either phase. I checked the Rockwell R651X datasheet. Different manufacturers may vary.
http://datasheet-pdf.com/datasheet/Rock ... 2.pdf.html

I met up with information that CMOS 65c02 stop the clock is possible.

Yes, the CMOS parts are different on the inside. I'm a bit vague on whether you can always stop them in either phase, but you can certainly stop them.

All CMOS ones allow stopping the clock with phase 2 high without losing data. WDC's can be stopped indefinitely in either phase.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I wonder why the various processors of that time (intel 8080, 6502, farchild F8) is defined minimum frequency - can not stop the clock, and can be eg. Stop signal RDY.
What is the reason?

Because transistors cost money, so a lot of the internal state is stored in single transistors, much like dynamic RAM. So it needs to be refreshed, which means running the clock.