I remembered that we had discussed accumulator register couple months ago. They may agree or disagree whatever they think 1 win-win or 0 win-win. I will like to revisit the discussion today.

I omit the pass gate transistor from top transistor's output and bottom transistor's output on the shared node. The pass gate transistor is not shown on the picture. Let's focus top transistor's input and bottom translator's input. We know that two omitted pass gate transistor's gate is connected to cclk (943) and SBAC (534). Both cclk and SBAC are set high at the same time. You always claim 0 win-win.

Go back and think two inputs. If two inputs are set low, then 0 win-win is always true. What will happen if two inputs are set high? 1 win-win is always true. The current comes from top transistor's output and bottom transistor's output on the shared node. Possibly, two currents collide in one node.

If top transistor's input is set high and bottom transistor's input is set low, then the current from bottom depletion transistor flows into top enhancement transistor. The output node is considered to be metastable. The metastable value appears to have weak low signal.

If top transistor's input is set low and bottom transistor's input is set high, then the current from top depletion transistor flows into bottom enhancement transistor. The output node is considered to be metastable. The metastable value appears to have weak low signal.

After you power up 6502 MPU, two accumulator register's depletion transistors receive power at the same time before two outputs will be 1s during the first cycle and they will be 0s during the second cycle and again, they will be 1s during the third cycle and again 0s so forth as their values are metastable.

The accumulator register's value will be stabilized with valid 0s or 1s from SBAC input after metastability ended.

Here is the picture.

Please comment what you think. I am interested to hear as soon as possible.

Bryan

What you have there [in the diagram] is something like a wired-NOR. The two pullups are in parallel, so they will act as a single, larger, pullup. So that's the logical function of a NOR, slightly more resistant to pulling down because more eager to pull up, and therefore the electrical threshold will be higher than it otherwise would have been.

You'll notice [in the 6502] that there are some unusually large transistors handling the databus input, to shift the logic threshold, this time towards lower voltages (the pulldown is much larger than the pullup)
http://visual6502.org/JSSim/expert.html ... 5&zoom=5.0

There's nothing metastable going on here.

Have you cranked up SPICE? That's an easy way to get circuit simulation. It's just about possible to simulate the whole CPU too. See viewtopic.php?f=4&t=2391&p=23864&hilit=spice#p23864 which leads us to
viewtopic.php?p=13550#p13550
(I'll see if I can fix the image there)
[Edit: I've provided the raw spice output file for download, so you can view the waves without needing to run the simulation]

Cheers
Ed

If a single, larger, pullup is true, then 1s flows into the single, shared node toward accumulator register while two inputs are low or one input is high and another input is low. If both inputs are high, 0s flows into the single, shared node, too.


Let's think about SR latch with two NORs. If set's input and reset's input are high, then two outputs are metastable while 0s are infinite. If set's input and reset's input are pulled low at the same time, then two outputs are metastable while 1s toggles 0s and toggles back 1s and toggles back 0s again each cycle. This is the same as I describe my diagram above and two NOTs and pass gate transistor in accumulator register.

I do not use spice. I can write input's value and output's value manually in MS Word or MS Excel. It helps me to understand how 0s and 1s work before I am able to write simulator in C++ source code. If logic gates use storage, update the input's value and output's value must be two times before output's value is valid. If logic gates are only transition without storage, update can be one time.

I am interested to see the raw spice output file as long as I do not need to run the spice.

Bryan

Sorry, I don't understand well enough what you're writing to help - I was responding to your image. If you tie together the outputs of two inverters, in MOS technology, you have a NOR gate.

Hi Ed,

Sorry, I could do my best in trying to explain what I am referring metastable value. My understanding is that metastable value does not have either 0s or 1s and it is considered to be invalid value. Sometimes, Q signal and Q' signal have same value while both of them are high or low at the same time.

Let's consider and you want to feed 14 MHz from osc chip into 6502 MPU chip's phase 0. One clock cycle out of 14 MHz clock cycle is 70 nanoseconds. Seventy nanoseconds is divided by two. CP1 (710) now runs 35 nanoseconds and another cclk (943) runs 35 nanoseconds.

You will not be able to see invalid value in accumulator register during cclk (943) as long as Q is 1 and Q' is 0 or Q is 0 and Q' is 1.

You will want to divide 35 nanoseconds by two. You are able to see invalid value in accumulator register during 17.5 nanoseconds (half cclk (943)) when Q and Q' are 1 or Q and Q' are 0. Another half cclk (943) invalid value now becomes valid value when Q is 1 and Q' is 0 or Q is 0 and Q' is 1.

I will need to update accumulator register two times in order to overwrite new data as valid value onto old data as invalid value when I write logic gate and timing simulator.

Here is my timing diagram. P is power. Q is special bus output. Q' is inverter of Q. C is cclk (943). S is SB/AC. D is data from special bus input through SB/AC's pass gate into accumulator register.

Look at the dark red vertical line. You will be able to see invalid value in Q and Q' during 17.5 nanoseconds and high and low cclk (943) is 35 nanoseconds.

Please comment if you agree that my timing diagram is accurate.

Bryan

So, if your circuit needs non-overlapping clocks, it's not enough to invert a clock and call that the inverse. What you do is use some cross-coupled gates, which allows a rising edge on each clock only when the other clock has gone to zero.

The 6502 does have an on-chip non-overlapping clock generator - that was one of the advances on the 6501 and the 6800. But it also has some places where a clock (or a clock-like signal) is simply inverted. It may even have some places where gate delay is important, which would mean a simulation has to iterate over several timesteps for each clock transition. It might be important as to the order in which the gates are evaluated, but in the case of visual6502, that turned out not to be an issue, as far as we know. We do know that some fine-tuning was needed in the evaluation function, to get everything working, and we know that the evaluation can take 20 steps or so before it converges on a result. It might be that a more sophisticated model would converge in fewer steps.

As a first approximation, your simulation should continue to evaluate until all signals are stable, before you can try to process the next clock edge. If it never stabilises, you have to do some investigation.

Cheers
Ed

Hi Ed,

I showed you the timing diagram. The NOR gate's two inputs are from Q (A0 register) and D (special bus). Two inverters of Q (A0 register) and Q' (A0' register) use cross-coupled gates. I mean to say that A0 inverter and A0' inverter operate at the SAME time to show invalid data before stabilizing to become valid data after power up.

It is possible that A0' inverter is evaluated to output data first before A0 inverter is evaluated to output final data. My simulator is able to evaluate two inverters and output two data at the SAME time. The iterator has to update two inverter's outputs in order to overwrite invalid data to become valid data.

My question is: is it possible to allow that real time circuit will perform two inverters and output two values at the same time unless two input's gates have the same length gates while current is flowing. If A0' inverter's gate is shorter than A0 inverter's gate, then of course, A0' inverter is performed first before A0 inverter. Do you understand what I am trying to say?

Bryan

The approach I'm most familiar with in simulators is that they do a lot of private work before updating the visible outputs. If you do show the result of every evaluation, I'd expect you will see a lot of glitches and oscillations on many signals before they reach a valid value. As mentioned, visual6502 can iterate some 20 or so times before reaching a conclusion - so, you should reckon on a clock phase being at least 20 gate delays, if you want to see all the intermediate transitions play out before the end of each phase.

The difficulty you may find, if you regard all the intermediate states as being physical states, is that somehow you need to update the charge storage for the dynamic latches. If you do that too quickly, you may find you discharged a node when the real chip does not discharge the node.

That is, the 6502 is not a collection of logic gates - it is a collection of transistors, and it uses charge storage. Most transistors can be resolved into logic gates, but not all. It could be - and I don't know the answer - that charge sharing is also important, when two undriven nodes are connected.

I'm afraid I will need more pictures to understand your exact queries - I know that's more work for you, but at present my brain hasn't the capacity to get a clear idea from your text. Sorry about that.