I'm keen to learn more about these issues, so could someone please educate me?

What are the implications for putting mask over a via? Why might it be bad, why might it be good? Since vias are never soldered, why does it matter? Is ElEctric_EyE's problem specific to the use of BGA packages?

My guess is this is a problem because the solder-paste will splurge into the vias, but if they were covered it wouldn't matter?

FWIW, the software I use (gEDA "pcb") produces covered vias by default, and it has never been something I've given much thought too...

Sorry for "newbie" questions...

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That's correct, but not so much as into the via hole. But an exposed via ring makes soldering totally impractical as the chance solder would hit the via is very high I would think. I wouldn't risk it personally.

EDIT: corrected language from 'via pad' to 'via ring'.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I found a discussion suggesting that soldermasking the whole via - including the hole - was possibly going to lead to trouble. So, leaving the hole in the middle might be safer, if it's possible, and just soldermasking the ring. But I really don't have the experience.

I gather there is also such a thing as a plugged via, where they put solder in the hole. Again, not sure what's best or what's normal.

Cheers
Ed

Yours is a 4-layer board, right, Sam? I would think that means vias would be "blind" (the hole doesn't go completely through) unless the via connects the very top layer to the very bottom layer. And in that case I bet the splurge problem would be real. But vias and pads are two slightly different things. I think you're not supposed to attach a component lead/pin to a via; that's the job of a pad. But sometimes the distinction doesn't matter.

Is that your main complaint, then -- that you risk shorts? I'm not sure I understand the issue(s) causing the disappointment.

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Sorry to add confusion, I corrected the language in my earlier post.

In the link I posted on the previous page, you can see in enso's pic, the via rings are masked. Also a few posts before his, Arlet's closeup of his board is the same.

Still awaiting EPCB's reply to my email.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Nothing silkscreened should go onto a hole, as it makes a bunch of the silkscreened paste squish through, whether solderpaste or soldermask. This is why you don't put vias in solder pads (unless you actually want a mess ). I was able to violate that rule on my memory modules because I solder them by hand, and I don't silkscreen solder paste onto them. I have no knowledge or experience in laying out boards for BGAs, but I suppose the chance of bridges underneath one would be greater if vias' rings are not masked; but then again you would want to put soldermask only on the ring, not pump it down the hole. Edit: Hmmm... I'll have to look up how LPI (liquid photoimageable) is done. They might spray a uniform coating onto it, including onto the holes, before using a photographic process to remove it where it's not wanted.

Multilayer boards don't usually have blind vias, since it adds a lot to the cost of making the board. The normal thing to do is have all vias go all the way through, so the manufacturer can laminate before drilling, then drill and thru-plate all the holes at once.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

(Direct link to enso's photo post:
viewtopic.php?p=25295#p25295
)
One way to think of the problem is that the vias placed between the pads are much closer than the next pad over - if the pads are about as close as you'd like to solder, then the vias are too close to be safe. If the via rings have a solder mask, they can't get involved with the solder.

I did read about an attempt to solder BGAs by placing an array of vias, one under each ball, and soldering from the back. I think it failed, because surface tension draws the whole ball inside the via and there's no connection to the package.

I still haven't received a reply from EPCB. I sent 2 emails from 2 different email accounts as they recommended... I'm registered on their Yahoo group, I may pose the question there.

Here is a real closeup of another version of a Spartan 6 upside down with the board behind it for comparison. It is a XC6SLX9-3FTG256I. I bought it awhile ago just to gaze at it, wondering if I could conquer it.
The FT(G)256 package has identical pinouts for the LX9, LX16, and LX25. I'm still waiting on the LX25's to arrive.
I'm trying to decipher the spec's for the FT(G)256 package on pg. 335 of UG385. Specifically, the symbols 'ddd' & 'eee'. Any ideas?
I'm tempted to try mounting this LX9, with just flux, and then just go ahead and test for shorts. It's a $28US part vs ~$50US for the LX25 part...

For reference, the board BGA pads are .020"(.508mm), and the FGPA balls are spec'd at .4mm (min) & .6mm (max).

(I wonder if that yellowish tint on the BGA solder balls is due to the silver/copper replacement of lead, since it's a FTG package)

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Are you contacting them through support@expresspcb.com? I've generally gotten a reply within two business days when contacting them through that E-mail address.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I'm guessing they are tolerances: ccc is flatness, ddd is conformity of the bottom surface of the balls to an ideal plane (so, flatness again), and eee is variation in ball placement(?)

And yes, it says the balls are tin/silver/copper so that explains the hue.

I received a reply from EPCB saying "I recommend that you read the ExpressPCB program's online help found under the "Help" menu. Look for the topic "Drawing on the Solder Mask Layers".

That would be the help menu within the PCB layout Program, which I read and states (for the benefit of others not using EPCB):
If I read this correctly, it tells one how to un-mask a section on the solder mask layer in order to expose the metal for soldering or connections, etc. by going to VIEW:OPTIONS:View top solder mask layer.
Not how to mask a section on the solder mask layer, which is which I need. No doubt me alone though...
Before I shoot back a friendly email, can you guys who use EPCB confirm this?

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I think you're right EE. It's frustrating when technical "help" people waste your time because they don't read the whole problem before firing off an irrelevant answer. Their software does not give you gerber files that you can edit, does it? If it does, you can brute-force a lot of things there, doing things your CAD was never designed to do.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I agree, but is it possible EE wasn't being very clear? Heck, I had trouble at first understanding what the complaint was.

Unfortunately, that bit from the Help section certainly isn't helpful -- no doubt about that. It's a shame when a project hits a setback like this.

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

You can only "remove" solder mask from a normally masked area. There is no function for extending the solder mask over exposed copper, so masking via is not possible.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

If the CAD makes gerber files, you can start another layer and put circles over the places you want masked, and copy-and-paste that layer's gerber data into the soldermask file for the particular layer, minding of course the %AD aperture definitions and %LPC*% or %LPD*% (layer polarity clear or layer polarity dark) directives. You can go back and forth between LPC and LPD as many times as you want in any given file. Another way to do it is that since they're all the same size and probably grouped together in the gerber file, you can just change the %AD directive in front of them to a different size to do the whole set at once. Gerber files are just text, and if you know what you're doing, it is very easy to do all kinds of modifications in them with a text editor. I do it on every board, shaving pads to get another trace through without violating my design rules, removing unneeded pads, adding or removing soldermask or solder paste, etc.. I add G04 comment lines to tell what each mod is. I check everything in the gerber viewer before sending it off. My CAD is so old it doesn't even put out gerber 274X files, only the old 274D, but I can change them over very quickly, and I can do some pretty complex stuff that the CAD was never intended to be able to do.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?