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ElEctric_EyE
PostPosted: Mon Dec 29, 2014 8:12 pm 
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Parts list started. Discrete components have yet to be added!
Was a challenge to find the 330MHz videoDAC part. :D


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12-29-2014 2-53-51 PM PVBV2 Parts incomplete.jpg
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GARTHWILSON
PostPosted: Mon Dec 29, 2014 8:26 pm 
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ElEctric_EyE wrote:
Garth, I interpreted your 'jagged' comment to mean diagonal so I tried to come up with a better layout:

I'm not sure what you mean by 'jagged' unless you're referring to the term "chainsaw" which just means there are cuts (regardless of shape) in what otherwise looks like a plane layer, in this case a power plane. As long as this layer doesn't get between your signal traces and the continuous ground plane, you'll be fine. Remember that any given signal trace's return current through the plane tries to run directly under that trace, taking the shape of the trace, but that if there's a cut in the trace, the return current has to take a different path and you end up with what amounts to an inductor or a stub depending on the length and width of the cut, and it degrades signal integrity. Actually, sometimes a cut in the plane, running perpendicular to the trace, is intentionally used to print an antenna on the board, something you don't want in this case. I really have no way of evaluating the effects for the particular application, so, since you're dealing with sub-nanosecond rise times for the fast, hi-res video stuff, I just shoot for next best, which we give the nebulous term "good engineering practice."

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ElEctric_EyE
PostPosted: Fri Jan 02, 2015 11:22 pm 
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I've finished the .ucf constraints file which assigns each pin on the FPGA a particular function for ISE to program the FPGA. This bit of work is abit mundane but it forces me to re-check pad-trace-pad IC interconnects. And I found a major problem that existed from early! Read on...
Code:
 # Spartan 6 XC6SLX25 Pin assignments on PVBV2a #  1.2.2015

 # Synchronous Ram #1 Signals #
NET "SRAddr[0]" LOC = PA4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //VREF
NET "SRAddr[1]" LOC = PA3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //VREF
NET "SRAddr[2]" LOC = PB3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[3]" LOC = PA2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[4]" LOC = PB2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[5]" LOC = PB1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[6]" LOC = PC6 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[7]" LOC = PD6 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[8]" LOC = PE7 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "SRAddr[9]" LOC = PD8 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[10]" LOC = PC8 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //VREF
NET "SRAddr[11]" LOC = PE8 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //N_GCLK
NET "SRAddr[12]" LOC = PE10 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "SRAddr[13]" LOC = PA8 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[14]" LOC = PB8 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[15]" LOC = PA7 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[16]" LOC = PC7 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[17]" LOC = PA6 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[18]" LOC = PB6 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[19]" LOC = PA5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[20]" LOC = PB5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[0]" LOC = PC1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[1]" LOC = PC2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[2]" LOC = PD1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[3]" LOC = PD3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[4]" LOC = PE1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[5]" LOC = PE2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[6]" LOC = PC5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[7]" LOC = PE6 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[8]" LOC = PD12 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[9]" LOC = PC9 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "SRD[10]" LOC = PA9 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //N_GCLK
NET "SRD[11]" LOC = PB10 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "SRD[12]" LOC = PA10 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //N_GCLK
NET "SRD[13]" LOC = PB12 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[14]" LOC = PA11 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[15]" LOC = PC11 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "SRD[16]" LOC = PC3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[17]" LOC = PE11 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRWEn" LOC = PE7 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "SRCLK" LOC = PF1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //N_GCLK

 # Synchronous Ram #2 Signals #
NET "SRAddr[0]" LOC = PP4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[1]" LOC = PT4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[2]" LOC = PR5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //D0-D15
NET "SRAddr[3]" LOC = PT5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //RDWR_B_VREF
NET "SRAddr[4]" LOC = PN4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[5]" LOC = PP5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //D0-D15
NET "SRAddr[6]" LOC = PF3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[7]" LOC = PE3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[8]" LOC = PE4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[9]" LOC = PH1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[10]" LOC = PG3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[11]" LOC = PG1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[12]" LOC = PD5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[13]" LOC = PN1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[14]" LOC = PN3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[15]" LOC = PP1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[16]" LOC = PP2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[17]" LOC = PR1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[18]" LOC = PR2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[19]" LOC = PM3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //VREF
NET "SRAddr[20]" LOC = PM5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[0]" LOC = PM4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[1]" LOC = PK6 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[2]" LOC = PL5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[3]" LOC = PK3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "SRD[4]" LOC = PK5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[5]" LOC = PJ4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //N_GCLK
NET "SRD[6]" LOC = PH4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "SRD[7]" LOC = PF4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[8]" LOC = PJ1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[9]" LOC = PJ3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[10]" LOC = PK1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[11]" LOC = PK2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[12]" LOC = PL1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[13]" LOC = PL3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[14]" LOC = PM1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[15]" LOC = PM2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[16]" LOC = PL4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[17]" LOC = PH2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRWEn" LOC = PF5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRCLK" LOC = PF2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
 
  # I2C Signals #
NET "SCL" LOC = PT9 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SDA" LOC = PR9 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O

# RGBin Signals #
NET "Rin[0]" LOC = PK16 | IOSTANDARD = LVCMOS33;  //A0-A25
NET "Rin[1]" LOC = PK14 | IOSTANDARD = LVCMOS33;  //N_GCLK
NET "Rin[2]" LOC = PL16 | IOSTANDARD = LVCMOS33;  //FCS...LDC
NET "Rin[3]" LOC = PM15 | IOSTANDARD = LVCMOS33;  //FCS...LDC
NET "Rin[4]" LOC = PN16 | IOSTANDARD = LVCMOS33;  //A0-A25
NET "Gin[0]" LOC = PP16 | IOSTANDARD = LVCMOS33;  //USER I/O
NET "Gin[1]" LOC = PP15 | IOSTANDARD = LVCMOS33;  //FCS..LDC
NET "Gin[2]" LOC = PR16 | IOSTANDARD = LVCMOS33;  //USER I/O
NET "Gin[3]" LOC = PL13 | IOSTANDARD = LVCMOS33;  //VREF
NET "Gin[4]" LOC = PN14 | IOSTANDARD = LVCMOS33;  //A0-A25
NET "Gin[5]" LOC = PT15 | IOSTANDARD = LVCMOS33;  //USER I/O
NET "Bin[0]" LOC = PR14 | IOSTANDARD = LVCMOS33;  //USER I/O
NET "Bin[1]" LOC = PT13 | IOSTANDARD = LVCMOS33;  //USER I/O
NET "Bin[2]" LOC = PT12 | IOSTANDARD = LVCMOS33;  //USER I/O
NET "Bin[3]" LOC = PP12 | IOSTANDARD = LVCMOS33;  //A0-A25
NET "Bin[4]" LOC = PN9 | IOSTANDARD = LVCMOS33;  //A0-A25
NET "HSYNCin" LOC = PT8 | IOSTANDARD = LVCMOS33 | SLEW = SLOW |DRIVE = 12;  //N_GCLK
NET "VSYNCin" LOC = PR12 | IOSTANDARD = LVCMOS33 | SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "PCLKin" LOC = PH5 | IOSTANDARD = LVCMOS33;  //N_GCLK


# RGBout Signals #
NET "Rout[0]" LOC = PA12 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //VREF
NET "Rout[1]" LOC = PA13 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "Rout[2]" LOC = PC13 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "Rout[3]" LOC = PA14 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "Rout[4]" LOC = PB14 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "Gout[0]" LOC = PB16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "Gout[1]" LOC = PC16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "Gout[2]" LOC = PC15 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "Gout[3]" LOC = PD16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "Gout[4]" LOC = PD14 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "Gout[5]" LOC = PE16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "Bout[0]" LOC = PE15 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "Bout[1]" LOC = PF16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "Bout[2]" LOC = PF15 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "Bout[3]" LOC = PG16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "Bout[4]" LOC = PH14 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "HSYNCout" LOC = PM6 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "VSYNCout" LOC = PR15 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "PCLKout" LOC = PJ16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //N_GCLK


 # Bi-Directional Communication Interface #
NET "D0" LOC = PL16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //FCS..LDC
NET "D1" LOC = PM16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //FCS..LDC
NET "D2" LOC = PN5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "D3" LOC = PT6 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "D4" LOC = PN6 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //D0-D15
NET "D5" LOC = PP7 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "D6" LOC = PT7 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //N_GCLK
NET "D7" LOC = PH16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "CommCLK" LOC = PM7 |IOSTANDARD = LVCMOS33 //N_GCLK
NET "R_W" LOC = PR7 |IOSTANDARD = LVCMOS33 //P_GCLK
NET "PVB1RDY" LOC = PP6 |IOSTANDARD = LVCMOS33;  //USER I/O
NET "PVB1BE" LOC = PP8 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK

 # Programmable Clock 1 Input from DS1085L  (Main Osc out 1 hardwired to J12)#

NET "ProCLKin1" LOC = PJ12 |IOSTANDARD = LVCMOS33;  //N_GCLK

 # Programmable Clock 2 Input from DS1085L  (Main Osc out 2 hardwired to J13)#

NET "ProCLKin2" LOC = PJ13 |IOSTANDARD = LVCMOS33;  //N_GCLK
 
 # Programmable Clock Output from K1 Controller Board #

NET "POSCin" LOC = PM9 |IOSTANDARD = LVCMOS33;  //P_GCLK

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ElEctric_EyE
PostPosted: Fri Jan 02, 2015 11:32 pm 
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Back on Dec 13 when I posted a pic of the PCB layout, a data bus trace was left unconnected. That was the 2nd iteration of the design. I realized this error at the final 6th iteration! Quite a PITA after the board fills up and things get tight after 2 more weeks of development. Errors like this make it a real challenge to re-route so many pad-pad traces! But I did it with some sort of inner pleasure. :twisted: I've got my finger on the trigger now for EPCB production. :)


Attachments:
wiring error.jpg
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PostPosted: Sun Jan 04, 2015 9:54 pm 
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I decided to do a few schematics for a few sections of the board.

The Power Supply Section is documented, that pic is next. I'm currently working on the FPGA SPI PROMs next. Finally, the Programmable Oscillator Section. A Block diagram will finish off the visual description of this design.

Comments/critiques welcome as always! You all have been a great help spotting bungling errors.

BOM is complete:


Attachments:
1-4-2015 4-36-28 PM.jpg
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ElEctric_EyE
PostPosted: Sun Jan 04, 2015 9:55 pm 
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Power Supply Section:


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PostPosted: Mon Jan 05, 2015 3:56 pm 
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FPGA SPI PROM MUX, JTAG and Programmable Oscillators. The DS1085L-5 programmable oscillators are programmed by an I2C bus, which (I almost forgot) uses external pull up resistors. The Spartan 6 user guide UG381, pg.35 spec's that lines with IOSTANDARD I2C are to be pulled to 3.3V through 1K resistors. I'll have to add these 2 resistors to the BOM and update the constraints file.

Also, there is a potential conflict if a user decides to push the Program at the same time an incoming FPGA Program signal is present from the Controller Board. A resistor is there with a TDB value to save an FPGA output pin from damage. Also, there is the fact that when U11 (DS1813) senses a low input (from either the switch or control signal), it holds the line low for 150ms.


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PostPosted: Mon Jan 05, 2015 8:46 pm 
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It's in their queue.
We'll see what kind of maker I am...
I'm breaking some PCB layout rules, which I've done before apparently successfully.
The last modification I went with was to use .5mm (.020") BGA pads instead of the recommended .4mm (.016") BGA pads.
My bypass caps are totally out of spec according to Xilinx UG393.
We shall see, *sigh*.
This is what happens in a design when there's a limited number of layers and board space!


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1-5-2015 3-32-46 PM.jpg
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PostPosted: Mon Jan 05, 2015 9:54 pm 
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I already see I could have shortened the HSYNC & VSYNC traces from the VGA connector to the FPGA, sh*t!
Already working on version i, just a few changes. It shouldn't hamper operation. I'll wait for further issues to develop before ordering PVBV2i


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PostPosted: Thu Jan 08, 2015 1:18 am 
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The boards are due by next tuesday.

So to try to coordinate the boards & parts arriving at similar times, I ordered most parts from the BOM. Just about everything has been ordered except the 2 SyncRAMs ($131US), as I am going to harvest them from 2 of the original PVBs. $131US saved there from the BOM...

Also, 2nd most expensive are the FPGA's @ $50 each. I did have to purchase 2 of the leaded versions of the S6LX25 from Avnet, because I've read that they're easier to mount to the board.

I'm really looking forward to this new experience of SMT "reflow" using solder paste+flux and a hot plate for the parts on top of the board. For parts on the bottom I expect to use the solder paste+flux, and hot air from my reflow station. I had always hand soldered the 0603 parts and .5mm QFP parts by hand with ultra thin solder!

I also have this USB microscope to help me out visually after reflowing.

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ElEctric_EyE
PostPosted: Mon Jan 12, 2015 11:06 pm 
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Just got my boards! 1 day early!
Spartan 6's XC6SLX25 wont arrive for 2 more days

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ElEctric_EyE
PostPosted: Mon Jan 12, 2015 11:37 pm 
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Focusing in on the 16x16 BGA pads...
Solder paste?! Are you Fin kidding me? Not meant for 1mm BGA pads with vias in the middle.


Attachments:
LX25 Production Pads.jpg
LX25 Production Pads.jpg [ 580.41 KiB | Viewed 1177 times ]

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BitWise
PostPosted: Tue Jan 13, 2015 8:23 am 
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Did you get a stencil with your boards? Some board shops provide them free if there are SMT pads on the board.

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BigEd
PostPosted: Tue Jan 13, 2015 9:52 am 
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Oh dear - is it normal to cover the via ring with soldermask?
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ElEctric_EyE
PostPosted: Tue Jan 13, 2015 12:14 pm 
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BigEd wrote:
Oh dear - is it normal to cover the via ring with soldermask?

This is going to cost me big time, at least I didn't bother to solder anything yet. Good eye Ed.
This topic came up before too, but I don't think I had fully realized... I don't feel too well.
I emailed EPCB support to see if it is at all possible to choose soldermask over a via.

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