Yes, it is possible to do that.
A smallish PIC connected to the 65C02 data bus could be used as a "blind loader" if it controls the 6502 'reset' and 'clock' lines. As described by Nicholas Fitzroy-Dale (link below), after the PIC resets the 6502 it pushes instructions to the 6502 that it needs to load RAM from a pseudo ROM image in Flash on the PIC. In this case the PIC is turning RAM off and on as necessary during each 6502 instruction cycle. Once RAM has been loaded the PIC resets the 6502 again and the 6502 runs entirely from RAM while the PIC simply provides a full speed clock.
You could do a two chip design by using a larger PIC, in terms of both number of pins and amount of memory, where the PIC shares its ROM, RAM, and I/O (serial port, SPI port, etc.) with the 6502. For example, a 40-pin 18F46K22 could be used to produce a two chip 6502 or 65C02 system with ~4K RAM, 60K ROM, plus serial and SPI ports, while clocking the 6502 at around 800-KHz.
Three chip designs (6502 or 65C02, RAM, and PIC) offer more RAM, slightly better performance (1-MHz), are easy to expand (VIA, ACIA, etc.), with features that can reduce overall system size and cost. Be sure to check out Jacob's three chip design (65C02, RAM, and PIC) in the link below. It features a 65C02 cpu, a PIC with programmable "soft decoder", 64K RAM, serial and SPI ports, and a 1-MHz clock.
Cheerful regards, Mike, K8LH
Links:
Nicholas Fitzroy-Dale's
Hardware SID Player article.
Andrew Jacob's
SB-6502/65C02 - A Minimal 6502/65C02 Computer.
