1080p PVB Custom Build #2: PVBV2

[ElEctric_EyE]

This thread continues from this older design.

I would've preferred to use a design utilizing 6 layers. I tried for a week to climb the learning curve after this post. Trying to learn new software in order to take advantage of another board manufacturer and many more board manufacturing variables is a F'in PITA... So, I now choose to make progress with what I know, i.e. 4 layers and Express ProtoPro PCB service. It has a limitation of 21 sq in. This new board will be 6.0"x3.5".

With a 256-pin 1mm BGA Spartan 6, I can still successfully route 149-pins out of the device that's available for user I/O in initial IC placement. 100 pins on top (red) and 49 on the bottom (green).
Each 2Mx18 SyncRAM needs:
21 address
18 data
8 control
Multiply the total by 2 for the 2 SyncRAMs, and the result is 94 pins are needed to interface the SyncRAMs to the FPGA.

Add 17 pins for the videoDAC and we're @ 111 pins total. Still 30+ pins of the FPGA to utilize some board space.

[ElEctric_EyE]

ElEctric_EyE wrote:

...Express ProtoPro PCB service. It has a limitation of 21 sq in. This new board will be 6.0"x3.5"...

PVBV2 will utilize the 3.8"x2.5" MiniBoard 4-Layer service for 3 boards for $98. The original PVB took advantage of this service... Gotta keep an eye on those holes from the very beginning! So far so good...
This is more like what the layout will look like.
The design is from an earlier chapter of the K1 Controller Board development where the XC6SLX25-3FT256 was to be the FPGA controller of choice. I started re-developing the layout for 3.8"x2.5" these last few days. Looks to be feasible:

[ElEctric_EyE]

Small update: 4-layer MiniBoard service isn't going to work. The design in the pic above already has 331 holes, only 19 left...
Not too bad of a situation though: The board will still remain the PVB original size of 3.8"x2.5",but using the 4-layer ProtoPro service I'll have an additional 300 holes which should be plenty to finish this PVBV2 design. The price will double to $200, but I'll get 4 boards instead of 3.
With memory parts I can salvage from 4 original PVBs, I should be able to have 2 PVBV2's up and running pretty quick, without spending too much.

Without going to the labor to show the progress of the board design, I'll just post the final version right before placing the order which will hopefully be in less than 2 weeks. There will be no feature creep on this design! Also, I'll post a block diagram of 1 PVBV2.

[BigEd]

EEye, you may have good reasons for sticking with your supplier, but for the benefit of others, I believe there are cheaper suppliers for this kind of project. (I only checked Seeedstudios. I assume their process is suitable and their quality is OK.) It's always true that a bigger board will cost more, but not all outfits charge according to how many vias are needed. There's a topic covering several suppliers at viewtopic.php?f=1&t=1913

Cheers
Ed

[Dr Jefyll]

Something not conspicuously mentioned on the Express PCB web site is the $38 courier-only shipping fee, which seems excessive compared with the Mouser ($20) and DigiKey ($8) courier charges. I was delighted with the boards I ordered from EPCB, but their business model... not so much. In the long term it'll clearly be in my interest to leave their hole restrictions and their locked-to-the-vendor CAD software behind.

Full disclosure: I'm actually cooking up another order for them right now! It's a rush job, and I reluctantly decided to let inertia prevail.

cheers
Jeff

[ElEctric_EyE]

BigEd wrote:

EEye, you may have good reasons for sticking with your supplier...
Cheers
Ed

The only good reason, (and I'm sure Jeff, BDD, 8bit and others can attest to this), is because the EPCB software was so damn easy to use from the beginning!
The hole limitation is a PITA, but the prices seem reasonably fair. But then they got ya by the b*lls.

I really wanted to learn the CADSoft Eagle program and I attempted it for about a week with my sights on utilizing eurocircuits.com as the 6-layer board manufacturer. But every single PCB tutorial I saw always started with a schematic, not from a raw PCB design. Almost like the schematic was mandatory as a first step to PCB design. I don't have time for that, not with so many pins/pads involved. If someone does come across a good Eagle PCB tutorial not involving schematics please let me know!

[Dr Jefyll]

Quote:

EPCB software was so damn easy to use from the beginning!

Too true! And I hope my remarks didn't seem to criticize you, EE. I'm in the same trap myself!

Quote:

But every single PCB tutorial I saw always started with a schematic, not from a raw PCB design.

I have the same complaint -- although I expect it's the tutorials which are lacking, not the software packages. IOW I expect you can do a seat-of-the-pants PCB layout. But the tutorials assume you'll start from a schematic.

The remedy, I believe, is to cobble up an ultra-simple schematic and use it as a test case. By the time the tutorial has led you from that to a finished PCB design, it should be apparent how the steps of the process fit together. At that point you'll know enough to start a new project directly at the PCB level.

-- Jeff

[BigEd]

Yes, I'm pretty sure you can just sketch a PCB layout. Of course you miss out on checking the connectivity using LVS. What we did - and we seem not to have published this - for the beeb816, was to have a script which generated an Eagle netlist from a simple verilog netlist. That way, we could simulate the verilog, LVS the board, and be pretty sure that the connectivity was right.

Here's a random example of a script file - it may not represent anything that works!

l1b_mk1.scr.txt

Illustrative Eagle netlist file as script

(6.3 KiB) Downloaded 189 times

Cheers
Ed

[ElEctric_EyE]

BigEd wrote:

... What we did - and we seem not to have published this - for the beeb816, was to have a script which generated an Eagle netlist from a simple verilog netlist. That way, we could simulate the verilog, LVS the board, and be pretty sure that the connectivity was right...

Cheers
Ed

That's too complicated, I don't need any rule checker. I need point A to point B routing plain and simple. I can check my own design...

I would expect the learning curve for this to be at least 6 months. Am I wrong?

[BigEd]

Our technique may be a bit unusual - shouldn't be too big a problem for someone already familiar with text processing, but of course it's not for everyone.

Jeff's suggestion is good: use the tutorials as they stand and you'll see how to use Eagle just as a PCB drawing tool.

Cheers
Ed

[ElEctric_EyE]

Gents, thanks for your recommendations, but I will continue with EPCB at this point. It is a tool that I know how to use successfully, especially for a design at this level.

[ElEctric_EyE]

Progress has been made on the board layout since Dec 13th. Nice and tight on 3.8"x2.5" 4 layers.

A few signals will have to be routed by manually soldering in 30AWG (common wirewrap) from point A to point B. These are for some low speed signals, like the Program button (S1) to FPGA (U1), but also some of the higher speed signals from the FPGA SPI FLASH PROMs (U5,U6).

Also, just above the 96-pin I/O connector are 20 signals present in an array of .031" vias. This array consists of 5 rows of 4 pins each spaced .1" apart horizontally, .05" vertically. They can be connected manually, i.e. by soldering wires to anything off-board or maybe to any of the 4 2 DS1085L (U7, U9 underneath) Programmable Oscillator outputs. The 3 vias in the array which are not labelled, but circled in yellow, are global clock pins. I couldn't let these FPGA pads go to waste just because the were unroutable!

[barrym95838]

It looks pretty nice EE, but the little engineer in my head tells me that your average trace length could likely benefit from rotating the FPGA and SRAM assemblage 90 degrees clockwise like so (rotating the actual chips 90 degrees as well):

Code: Select all

              OS           OS           OS
                    SRAM        SRAM
                     U3          U2
              OS          FPGA          OS
                 U9  U7    U1      U4
                 +======== I/O ========+

... where OS stands for "other stuff".

I know, I'm a stinker for even bringing it up at this stage of the game, but that little engineer in my head wouldn't leave me alone!

Mike

[Rob Finch]

Quote:

Each 2Mx18 SyncRAM needs:
21 address
18 data
8 control
Multiply the total by 2 for the 2 SyncRAMs, and the result is 94 pins are needed to interface the SyncRAMs to the FPGA.

Just curious, could the address lines be shared on the RAMs or is it a bad idea ?

[BigDumbDinosaur]

barrym95838 wrote:

It looks pretty nice EE, but the little engineer in my head tells me that your average trace length could likely benefit from rotating the FPGA and SRAM assemblage 90 degrees clockwise like so (rotating the actual chips 90 degrees as well):

Code: Select all

              OS           OS           OS
                    SRAM        SRAM
                     U3          U2
              OS          FPGA          OS
                 U9  U7    U1      U4
                 +======== I/O ========+

... where OS stands for "other stuff".

I know, I'm a stinker for even bringing it up at this stage of the game, but that little engineer in my head wouldn't leave me alone!

Mike

The beauty of a paper PCB is that it costs nothing other than a bit of time to build. Better to make the changes before the boards have been produced than afterward.