R65C02 data bus sharing
R65C02 data bus sharing
Hi! I'm building my first 6502 computer and I've got a question. In my design the 6502 shares address and data busses with a co-processor (actually an AVR MCU). I have a Roswell 65C02 and since it can't tristate the address bus I'm using two 74HC541s to detach the 6502 from the address bus while the co-processor is active.
My question is about the data bus. If I hold the 6502 in reset or halt the CPU using RDY, do I need a buffer on the data bus? I'm assuming the 6502 only drives the data lines when storing to memory, right? But, e.g. what happens in the case the CPU is executing a store instruction and the CPU is halted by pulling RDY low? Does the 6502 release it's grip on the data bus in this case?
EDIT: btw. a great forum you have here!
My question is about the data bus. If I hold the 6502 in reset or halt the CPU using RDY, do I need a buffer on the data bus? I'm assuming the 6502 only drives the data lines when storing to memory, right? But, e.g. what happens in the case the CPU is executing a store instruction and the CPU is halted by pulling RDY low? Does the 6502 release it's grip on the data bus in this case?
EDIT: btw. a great forum you have here!
- GARTHWILSON
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Re: R65C02 data bus sharing
Unlike the NMOS 6502, the 65c02 will stop even on writes when RDY is negated (which, since it is positive logic, means pulled down). When you're ReaDY to get going again, pull RDY up.
Modern WDC 65c02's do have a BE (bus-enable) pin (pin 36 if it's the DIP), so you can omit the 74xx541's.
I have a 6502 primer at http://wilsonminesco.com/6502primer/index.html in 22 sections covering many aspects of building a 6502 computer.
Modern WDC 65c02's do have a BE (bus-enable) pin (pin 36 if it's the DIP), so you can omit the 74xx541's.
I have a 6502 primer at http://wilsonminesco.com/6502primer/index.html in 22 sections covering many aspects of building a 6502 computer.
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?
Re: R65C02 data bus sharing
Thank you Garth! I've been indeed reading your 6502 primer, excellent articles!
Ok, it should be ok to use the data bus while the MPU is halted by pulling RDY down. Does the same apply to reset? I.e. if I pull reset down, data bus gets released?
Ok, it should be ok to use the data bus while the MPU is halted by pulling RDY down. Does the same apply to reset? I.e. if I pull reset down, data bus gets released?
- GARTHWILSON
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Re: R65C02 data bus sharing
I'm sure the processor releases the data bus on reset, but I never had any reason to test it. Note that pulling RDY low is just slow memory telling it, "Hold on-- I'm not ready yet. I need more time. Please hold the current state longer." So if you're writing, the processor will keep asserting the data bus while RDY is low.
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?
Re: R65C02 data bus sharing
Ok, I'll test it this weekend. Many thanks!
EDIT: does someone happen to know how to get a W65C02 or two shipped to Finland in a reasonable amount of time without outrageous shipping costs…?
EDIT: does someone happen to know how to get a W65C02 or two shipped to Finland in a reasonable amount of time without outrageous shipping costs…?
- GARTHWILSON
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Re: R65C02 data bus sharing
Check the 65xx parts sources sticky topic at viewtopic.php?f=1&t=1953 which we try to keep updated.
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?
Re: R65C02 data bus sharing
phvic wrote:
does someone happen to know how to get a W65C02 or two shipped to Finland in a reasonable amount of time without outrageous shipping costs…?
BTW as an alternative to using the RDY input to start & stop the 'C02, you could arrange for the AVR to generate the signal that serves as the 'C02's clock input (on pin 37). (In other words, don't use an oscillator). It's just something to consider -- I don't know what your priorities are; perhaps there's no advantage.
If you go this route, you can ignore R/W. Read or write, the CPU never drives the data bus during Phase 1. So when you stop the clock, just stop it in the low state (Phase 1).
Good luck, welcome, and keep us posted on your progress!
Jeff
ps- Rockwell datasheet attached. Note the 'c112 variant can only be used with an external clock, such as from the AVR.
- Attachments
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- R65C02 (Rockwell).pdf
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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html
https://laughtonelectronics.com/Arcana/ ... mmary.html
- GARTHWILSON
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Re: R65C02 data bus sharing
Only WDC's can be stopped during phase 1 though. Rockwell's can't.
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?
Re: R65C02 data bus sharing
GARTHWILSON wrote:
Only WDC's can be stopped during phase 1 though. Rockwell's can't.
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html
https://laughtonelectronics.com/Arcana/ ... mmary.html
Re: R65C02 data bus sharing
Yeah, I only have a Rockwell 65C02 without the BE pin at the moment. I'm probably going to use the WDC version, if I can obtain one, in the final version to save PCB space. I'm using Eagle so it could be a tight fit to get all components and traces on one homemade single-sided PCB.
I've just finishing wiring the thing up on a breadboard and I'm writing a test firmware for the AVR. We should get some results soon
EDIT: Roswell -> Rockwell
I've just finishing wiring the thing up on a breadboard and I'm writing a test firmware for the AVR. We should get some results soon
EDIT: Roswell -> Rockwell
Last edited by phvic on Sat Nov 22, 2014 9:33 pm, edited 2 times in total.
Re: R65C02 data bus sharing
Dr Jefyll wrote:
Good luck, welcome, and keep us posted on your progress!
Re: R65C02 data bus sharing
phvic wrote:
I've just finishing wiring the thing up on a breadboard and I'm writing a test firmware for the AVR. We should get some results soon 
I've done simple single sided PCBs myself, but nothing as complex as a 8 bit computer. A few around here have though, eg. lordbubsy's MARC-1 computer: viewtopic.php?f=4&t=2756
PS. Welcome!
8 bit fun and games: https://www.aslak.net/
Re: R65C02 data bus sharing
Ok, small update: proof of concept works! AVR pulls reset down, acquires bus access, updates SRAM, releases bus and starts generating clock signal for 6502. Next I'll try to use RDY to interleave SRAM accesses from AVR and 6502.
Gotta get some sleep now, later!
Gotta get some sleep now, later!
Re: R65C02 data bus sharing
Aslak3 wrote:
phvic wrote:
I've just finishing wiring the thing up on a breadboard and I'm writing a test firmware for the AVR. We should get some results soon 
I've done simple single sided PCBs myself, but nothing as complex as a 8 bit computer. A few around here have though, eg. lordbubsy's MARC-1 computer: viewtopic.php?f=4&t=2756
PS. Welcome!
Re: R65C02 data bus sharing
Just to make sure I'm not doing anything wrong: is it ok to hardwire SRAM's OE to ground? From what I've gathered, it seems that SRAMs don't care about OE during writes.
phi2 clock would be connected to SRAM's CE through an inverter to prevent accidental writes when phi2 is low.
Did I get this right?
phi2 clock would be connected to SRAM's CE through an inverter to prevent accidental writes when phi2 is low.
Did I get this right?