Aside from the discrete bits for the reset circuit, and the 1.8 MHz crystal (used for both the UART clock and for the main CPU clock), the breadboard holds:
- A WDC 65816.
- Two 74HC132 quad schmitt-trigger NANDs.
- A 74HC245 to keep the bank address from colliding the data bus.
- A 74HC573 to latch the low five bank address bits (it also latches the upper three bits, but those aren't currently used).
- A 32kx8 RAM of some sort.
- An SST39SF040 512kx8 FlashROM in a ZIF socket.
- A 16550A UART.
There is ample board space and address space to add a VIA, though doing the address decoding reasonably looks to require a '138. Adding a '138 would also allow mounting a second ROM for in-system programming purposes or just having more storage capacity, and would still leave quite a bit of address space open (and conveniently-decoded).
My next steps are to work out an initial test program and to improve my (arduino-based) FlashROM programming setup to the point of being actually usable rather than a proof-of-concept for getting data onto a ROM. Eventually I want to do a more-permanent (wire-wrap) version, but there doesn't seem to be much point until I have something running on a breadboard.