That's the animal. It's available in PLCC-84, TQFP-100, PQFP-100 and PQFP-160 packages. I'm not able to solder the PGFP and TQFP packages, so I stuck with the PLCC-84 for now.
Have you considered radically reworking the board...?
No. The west side of the board has to remain unchanged from POC V1 so the SCSI host adapter (HBA) will fit. Otherwise, I will be faced with redesigning the HBA as well and spending extra money to get new PCBs made. The HBA works very well, so I really don't want to tinker with it for now.
I'm curious to learn what BDD will be programming the device to do. The XC95108 in my micro (a comparable part I believe) serves as a couple of simple peripherals (sounder driver, bank switching latch, IDE high byte latch) as well as the traditional glue functions (address decoding, interrupt routing, etc). I'm interested to find out what BDDs PLD will be handling. Eg those unuseable pins could be useful for all kinds of things.
The ATF1504AS (the PLCC-44 device) was supposed to handle memory mapping, bank address capture, SCSI DMA logic, wait-state generation,
/RD and
/WD generation, and I/O device selection. The 1504 has 64 macro cells, so I also was planning on synthesizing a simple "hardware management unit" (HMU) to allow selective mapping out of low and high ROM, as well as write bleed-through when a ROM address is written. This would have allowed me to shadow the ROM in RAM and avoid wait-stating ROM accesses at high clock rates.
Since it appears I will have to make the switch to the 1508AS, the door will be opened to a more elaborate design. Here's the memory map:
- POC V2 Memory Map
Ultimately, the HMU would be as follows:
- Hardware Management Unit Assignments
The extra I/O pins on the 1508 can be connected to
ABORTB,
IRQB,
NIMB and
VPB. With 128 macrocells, I'll have adequate resources to implement some memory protection, user and supervisor modes, bank $00 remapping and other features that I've hashed out in older posts.
