OK... sorry about the delay.
Every chip will have pins called Vcc or Vdd, and pins called GND or Vdd. They're usually not marked on schematics, because they just clutter things. You're assumed to know that Vcc and Vdd connect to the power supply +5V, GND and Vdd to the power supply return (0V or ground or whatever it is called). It won't work at all if you forget any of them.
The later schematic has U3:15 connected to ground, not the clock. I'll have to check a few datasheets to see if that will work correctly. I remember using the clock signal in the address decoding logic last time I build a 6502 board, but it might be possible to do it without.
The connections for CTS and DCD don't really matter, unless you write software that uses them.
The connections on U7 that you list don't matter much either, unless you're using them. They won't stop anything from working.
The rest of the connections you list don't make any sense at all, in either version. Address lines are usually connected to each other (A1 to A1, A2 to A2), with the higher ones on the CPU (U1) going through decoding logic (U2 and U3) to the memory chip selects. I suspect the wire-wrap list is for a different memory chip with a different pinout.
I've been looking at
http://www.hytherion.com/beattidp/compu ... iy6502.pdf which appears correct. I can't see any obvious problems with it, at least.
The first thing to do is to check that every chip is connected to the power supply, and that the supply is giving you 5V. Probably best to do that before you put the chips in the sockets - I managed to get the power supply backwards once, and that was not good (but those old NMOS 6502s are TOUGH. The board survived 30 seconds of backwards power without a scratch).
Then check that there's a clock signal on U1:37 (logic probes usually have three lights - one for "0", one for "1", and the third for oscillating signals. If it only has two lights, they should both be lit for the clock).
Make sure reset (U1:40) goes high slightly after power is applied. I don't like that reset circuit much - I'd be happier with a 7414 (is that the number? It's been so long) schmitt inverter in between (with the positions of the capacitor and resistor swapped, and the button pulling it to Vcc instead of GND). But if it works for him, we'll leave it.
Then make sure the address lines are changing. If you remove U4, U5, U6, and U8 from the board, you can be rather rude and connect the data lines to +5V or GND to put a NOP instruction on the data bus ($EA = 11101010. So D0 to GND, D1 to +5V, and so on). That will make the processor act as a counter. A0 will toggle very quickly, A1 at half the speed, A2 at half the speed of A1, and so on. You probably won't be able to see even A15 toggling (14Hz by my calculation), but both lights on the logic probe should be on.
Then put all the chips back, and check U5:20 (the ROM's chip select). It should be going up and down. The data lines (D0 to D7) should be going up and down too - that means you're getting code out of the ROM.
I'd start with a very simple program in the ROM too. At the start, just a loop. Make sure you've got the reset vector pointing to the right place. The ROM will be mapped to the top of memory. Then write one that sets a 6522 port to output and toggles one of the bits. Check the 6522 chip selects (U8:23,24) and R/W (U8:22). They should be bouncing up and down. Make sure your selected output is toggling.
If any of these checks fail, then it's time to do more detailed investigation in that particular area.
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