6502 can be faster than 68k :-)

[yzoer]

Little tidbit I came across this afternoon while trying to decide whether or not I should move up to a 68k for my next project or a 6502. So one thing I'll be doing a lot is writing data to registers. In 68k, writing a 16-bit word in the form of move.w #xxxx,0(a0) takes 16 clock cycles.

On the 6502 on the other hand, you'd have one lda #imm, which takes 2 clocks, following by (alright, I'm cheating here b/c I'm writing to zeropage, but still) an sta zp, which takes 3 clocks. Given you need two of those back to back, you get 5*2 = 10 clocks, or SIX clocks faster! Memory footprint is the same, interestingly enough...

Not too shabby, especially when you consider you can run them up to 14mhz or so now!

-Yvo

[GARTHWILSON]

Wow. 14MHz is a pretty conservative rating for modern 6502's though. According to WDC, the off-the-shelf ones generally top out at about 25MHz @ 5V if the supporting parts cooperate. (There are '02 cores inside custom ICs running over 200MHz though.) The off-the-shelf 65816's maximum clock speed is slightly lower but there was the C64 accelerator with the '816 that ran at 20MHz, and if there was some fallout, I don't think they could have had a viable market product. LDA#, STA___ on the '816 in 16-bit-accumulator mode would take 7 clocks for direct page, 8 for abs. At 20MHz, that's 350 or 400ns. The 65c02 and '816 are still in production with no end in sight. Can that be said for the 68K?

[yzoer]

Oh reaaaaaaaallly?

Unfortunately I'm bound (well, maybe not) by the speed of my SRAM, which hovers around 70ns, which just hovers under half my master clock (25mhz) access. Meh, it's plenty though... Just thought it was interesting as your first gut check is to go with the bigger / better one. That said, a 16mhz Freescale 68k from Digikey will set you back almost $16 whereas a 65c02s comes in at around half that.

I guess bigger isn't always better

-Yvo

[GARTHWILSON]

SRAM in 10-15ns is common, but regardless, remember to leave time for glue logic and set-up times. I think (E)EPROM faster than about 55ns is very rare.

[White Flame]

Well, you're also comparing writing a 16-bit word on a 68k to writing an 8-bit word on a 6502. If you're consistently using word-sized data, you might think about upgrading... to an '816.

[barrym95838]

There was a bubble sort benchmark in a book that I read back in the 80s on the 'new' 16-bit microprocessors. It compared the 8086, 68000, Z8000, 9900, LSI-11, and 16032. I coded the benchmark on my 1 MHz Apple ][+. For 200 16-bit integers in worst-case order, the 6502 compared very favorably with all of them, cycle-for-cycle. 6502 machine code density was meh, but cycle count was close to the best, even with the disadvantage of dual-stage compares and swaps. Here's the back cover ... it's a bit dog-eared from heavy use.

Mike

[BigDumbDinosaur]

barrym95838 wrote:

There was a bubble sort benchmark in a book that I read back in the 80s on the 'new' 16-bit microprocessors. It compared the 8086, 68000, Z8000, 9900, LSI-11, and 16032. I coded the benchmark on my 1 MHz Apple ][+. For 200 16-bit integers in worst-case order, the 6502 compared very favorably with all of them, cycle-for-cycle. 6502 machine code density was meh, but cycle count was close to the best, even with the disadvantage of dual-stage compares and swaps. Here's the back cover ... it's a bit dog-eared from heavy use.

Scan1a.jpg

Mike

Guessing either the 65C816 wasn't yet on the scene or the editors at Sams had not heard of it.

[BigDumbDinosaur]

GARTHWILSON wrote:

SRAM in 10-15ns is common, but regardless, remember to leave time for glue logic and set-up times. I think (E)EPROM faster than about 55ns is very rare.

There are sources for 45ns OTP PROMs (I have a few here), but the extra 10ns won't help much when the Ø2 clock is cranked up to the max.

[BigDumbDinosaur]

yzoer wrote:

Oh reaaaaaaaallly?

Unfortunately I'm bound (well, maybe not) by the speed of my SRAM, which hovers around 70ns, which just hovers under half my master clock (25mhz) access. Meh, it's plenty though... Just thought it was interesting as your first gut check is to go with the bigger / better one. That said, a 16mhz Freescale 68k from Digikey will set you back almost $16 whereas a 65c02s comes in at around half that.

I guess bigger isn't always better

-Yvo

Time to upgrade that SRAM. I used 128Kb × 8 10ns SRAM in my POC units. Even faster versions can be gotten, but 10ns will suffice for a system running at up to 20 MHz if the glue logic isn't slow.

[barrym95838]

BigDumbDinosaur wrote:

Guessing either the 65C816 wasn't yet on the seen or the editors at Sams had not hear of it.

Correct. Copyright 1981. The N.S. 16k was still vapor-ware, but received the most oohs and ahhs from the authors, or so it seemed. I think that it wound up with the shortest lifespan of all of them.

Mike

[yzoer]

BigDumbDinosaur wrote:

yzoer wrote:

Oh reaaaaaaaallly?

Unfortunately I'm bound (well, maybe not) by the speed of my SRAM, which hovers around 70ns, which just hovers under half my master clock (25mhz) access. Meh, it's plenty though... Just thought it was interesting as your first gut check is to go with the bigger / better one. That said, a 16mhz Freescale 68k from Digikey will set you back almost $16 whereas a 65c02s comes in at around half that.

I guess bigger isn't always better

-Yvo

Time to upgrade that SRAM. I used 128Kb × 8 10ns SRAM in my POC units. Even faster versions can be gotten, but 10ns will suffice for a system running at up to 20 MHz if the glue logic isn't slow.

Yeah, but most of those don't come in DIP packages

45-70ns is plenty fast when you register the address / data lines. While that does mean you have to account for an extra cycle or two in latency, you get a rock-solid system. I'm dividing my 25mhz master clock down to 12.5mhz (80ns period) which means I can use the slowest, readily available DIP ROM/RAM.

-Yvo

[GARTHWILSON]

yzoer wrote:

45-70ns is plenty fast when you register the address / data lines. While that does mean you have to account for an extra cycle or two in latency, you get a rock-solid system. I'm dividing my 25mhz master clock down to 12.5mhz (80ns period) which means I can use the slowest, readily available DIP ROM/RAM.

From the address-decoding page of my 6502 primer:

• • Note that 100ns memory is not fast enough for 10MHz on a 6502! It's only a slight oversimplification to say that the 6502 basically does a memory access in half a cycle, meaning 50ns @ 10MHz, 500ns @ 1MHz, etc., and some of that time will be taken up by glue logic, set-up times, etc., leaving less than you might think for the memory itself. In fact, the Apple II did two memory accesses per cycle, two million per second at 1MHz, with the video accessing the memory during the first half of Φ2, and the processor during the second half, interleaving, so both could access the same memory at the same time at full speed, with no conflicts. Anyway, speed is not just the inverse of the access time.
    
    To expand on the senario above, consider 100ns memory (let's say it's ROM, so we can leave Φ2 out of it) and a 10MHz 6502. One period at 10MHz is 100ns; but from there you have to subtract the specified address setup time (tADS, 30ns for a 14MHz 6502) and the read data setup time (tDSR, 10ns for a 14MHz 6502) and probably some address-decoding logic time, let's say 10ns but it will depend on your circuit and how fast your logic is, leaving you with about 50ns for the ROM at 10MHz. If you're running it at 3.3V, the spec.s say you need to take off another 15ns, leaving you with ROM that can dish up the data in 35ns @3.3V. That's if you want to be sure the product will always work. It's nice to know that parts are usually faster than the guaranteed worst case; but for production, you can't assume they always will, because at any time the suppliers could give you slower parts that are still within spec and they won't work at your speed and it won't be any fault of theirs!

[yzoer]

That's an excellent point there which is easily overlooked, as I just did

The z80 has a much longer memory cycle which allows for a lot more wiggle-room. Not so on the 6502! I'll have a proper look at the 65c02s datasheet to see what my options are. Worst case, I can always run it slower but I'd rather not

-Yvo

[GARTHWILSON]

That's part of why it outperformed the Z80 in spite of its fewer and smaller registers and its lower clock speed.

Do read the 6502 primer. It's big and takes time, but it will save you far more time.

[yzoer]

Thanks Garth..

Yeah, I'll give it a read. I never really got into the 6502 hardware side of things and have mostly done z80 hardware which, like I said earlier, is a lot more forgiving. Of course, that comes at the price of lackluster performance. I'm beginning to see now why a lot of old arcade boards used a z80

It actually doesn't look that bad. I should be able to get it to run reliably at 6.125mhz (160ns period) with 70ns ROM/RAM. Here's a link to a somewhat clearer picture about the read/write timing from NutsAndVolts.

http://www.atarimagazines.com/computeii ... /page9.php

The numbers are somewhat bigger but hey, it's 23 years old!

-Yvo