BitWise wrote:
When a CPU is reset (or switched on for the first time) it will begin executing code from a location that either fixed in the CPU's design (i.e. a Z80 starts at location 0x0000) or defined by a 'vector' (e.g. an address value) stored at a specific location (i.e. the 6502's reset vector at 0xfffc), so normally you must have a small amount of ROM which is accessible on reset.
Often this ROM contains a simple 'bootstrap' program which accesses a device like a floppy or a hard drive and reads more program code into memory from a fixed location (i.e. the first few sectors of the disk) and executes it. Often several stages of bootstrapping, each more sophisticated than the last, are needed before you have all the code needed for a complex operating system to be loaded into RAM and fully initialised.
The above is the pattern followed by my POC unit. The BIOS ROM contains enough code to load a boot block from SCSI disk $00 and execute the code therein. The only significant difference is that the same ROM also has a machine code monitor, which acts as a primitive "operating system" if the load-from-disk fails to start a real one.
Quote:
Most CPUs can be kept in a frozen state by means of some control pins, for example by holding the 6502's reset pin LO does this. This means that another device can take control of the address, data and control lines to write into memory at the location where the boot ROM would normally be.
Another way to do this is by asserting the 65C02/65C816 RDY and BE inputs to halt and tri-state the MPU. The data sheets do not indicate (or even imply) that the MPU goes to tri-state while RESETB is being held low. It's conceivable that inadvertent bus contention could occur while the other device is writing to RAM.