CHOCHI - an inexpensive FPGA board with 128K SRAM

[enso]

Note: this top post will be updated as needed
Current version: CHOCHI H.
Assembled boards available. PM me...
Summary: CHOCHI is a minimal XC3S50 FPGA board with 128K of fast SRAM and 31 IO pins, capable of hosting Arlet's 6502 core with up to 128K RAM with about 1/2 the resources available for custom circuitry. It is closely related to DILDAR50 viewtopic.php?f=10&t=2638- in fact the upper IO connector is identical in later boards. Final prototypes of CHOCHI even carry the DILDAR insignia.:

For more information also visit http://apple2.x10.mx/CHOCHI

Motivation
CHOCHI was driven by the desire for a minimal, inexpensive 6502 controller that is more capable than DILDAR50 (more than 8K of RAM). CHOCHI, in its minimalism, matches the spirit as well as the requirements for retrocomputing. It is big enough to fit a full 6502 system (including serial, parallel, and in the future, SD card and video interfaces). Working with it requires a minimal mindset that we are familiar with and the rest of the world finds absurd. And it helps that it is inexpensive enough to be nearly disposable.
Minimal Requirements
The board requires a regulated 3.3V power supply, and a 115,200 serial port connection to your PC. A terminal program capable of sending binary files directly is also needed (I use gtkterm on linux).
Skill level
To use this board you need to be reasonably comfortable hooking up and configuring a serial port on your computer, be able to compile or assemble 6502 code. Minimal soldering skills are required to connect to IO ports. Advanced users may reconfigure the FPGA to fine-tune the system to their liking, or do something completely different.
Availability
As an experiment I am happy to offer members of 6502.org assembled boards for about $35. PM me if you are interested. Open source access to all Verilog and design files (gEDA PCB); all files CHOCHI files created by me should be considered as public domain if your country accepts it, or a compatible open license of your choosing.
Design notes
CHOCHI started its life as DILDAR50. The bottom IO connector was removed and IO recycled to connect the SRAM. Two remaining pins were used as a dedicated serial connector (lower right). Unlike DILDAR, the power regulators are right on top. There are no parts on the bottom, making it much easier to manufacture. The board can actually accomodate a 512K SRAM.
Initial configuration
The board comes pre-configured with a 45MHz 6502 core (Arlet's) with almost 64K RAM (and some IO). The system boots into a loader on power-up. The initial configuration features
-LED output ($C000, also top left pin)
-UART ($C008, special pins, 115200 baud, no parity, 2 stop bits works best)
-8-bit output port ($C010, top row right side)
-8-bit input port ($C018, bottom row, right side)
-Reset button port(2nd top pin from left)
Memory Map

Code: Select all

$0000-$01FF  BRAM
$0200-$BFFF  SRAM
$C000-$C0FF  IO
$F800-$F9FF  Mapped to $0000-$01FF
$FA00-$FFFF  BRAM, upon bootup contains loader and vectors

6502 software
Link to FIG-FORTH post: viewtopic.php?f=10&t=2644&p=28311#p28311
The loader accepts a binary file prefixed by 16-bit address and 16-bit size. So far I managed to get Daryl's monitor, Fig-Forth and EhBASIC running, with a little help from my friends here. Thank you.

[barrym95838]

Nice looking little unit, enso! Do you have any "action" pix, showing it connected to some peripherals?

Mike

[Arlet]

enso wrote:

One of my tests implements a 45MHz 6502 core (Arlet's) with almost 64K RAM (and some IO).

Assuming that the SRAM runs at 100 MHz (can you add link to datasheet), it should be possible to run the core faster, but with some extra RDY states to accommodate memory latency. Overall, it should go faster than 45 MHz.

[enso]

Here is a sexy action shot:

You can see the LED is on (it's running a blinky test).

The rainbow cable is the JTAG connection. An FTDI Basic USB-serial board is attached to the serial port. The pins are soldered facing up for easy testing (and wire wrapping), but may be soldered down.

I am drawing 3.3V from a nearby Digilent Spartan-3 board.

[enso]

Arlet wrote:

Assuming that the SRAM runs at 100 MHz (can you add link to datasheet), it should be possible to run the core faster, but with some extra RDY states to accommodate memory latency. Overall, it should go faster than 45 MHz.

I have no doubt that there is a way to make it run faster. With internal BRAMs Arlet's core ran as fast as 105MHz (although it may not be stable over 100MHz, more tests needed).

Here is the datasheet for the SRAM:

K6R1008V1C-JC10.pdf

(132.3 KiB) Downloaded 545 times

The SRAM controller code may not be optimal - perhaps someone could improve it...

Code: Select all

/******************************************************************************
 a controller for a 128K SRAM. 
******************************************************************************/
module mSRAM128K(
  input sclk
, input en              //1 means do enable;
, input we
, input  [16: 0] ab
, input  [ 7: 0] di
, output reg [ 7: 0] do
// interface to the real chip
, output [16: 0] xab
, inout  [ 7: 0] xdb
, output  xcs_
, output  xoe_
, output  xwe_
);
  assign xcs_ = ~en;    //chip select is inverted
  assign xwe_ = ~we;    //we is inverted
  assign xoe_ = 0;     //output on (low) when reading
  assign xab  = ab;     //address bus permanently connected
  //
  // Implement a tri-state circuit for the inout xdb
  wire [7:0] xin = we ? 8'bZ : xdb[7:0] ; //on read, let data in    
  assign xdb[7:0]     = we ? di[7:0]   : 8'bZ; //on write, let data out  
  //
  // Return read result next cycle
  always @ (posedge sclk)
    if(en & ~we)  //on write, output 0 - for some reason it's FF
      do[7:0] <= xin[7:0];
    else
      do[7:0] <= 8'h00;
endmodule

[Tor]

What is needed for programming this board? Or installing Arlet's 6502 core? How would one (after installing the core) then use the board, i.e. connect it to the world? As you may understand I have no experience with FPGA, except for a Z80 board I have where there's a Spartan FPGA which can be updated from an SD card via a monitor program running in the Z80.
I'm very interested in your board if I could just be able to use it!

-Tor

[enso]

Tor wrote:

What is needed for programming this board? Or installing Arlet's 6502 core? How would one (after installing the core) then use the board, i.e. connect it to the world?...

--------------------------------------------------------------------------------------------------------
I can pre-configure the board with Arlet's core and a loader. The FPGA then boots up into a prompt and waits for code to be uploaded via serial, using a very simple binary format: the binary has a 16-bit address and a 16-bit size in front. I use Kingswood assembler to output a binary file. For instance, FIG-FORTH, based at $0800 required the following code in the beginning

Code: Select all

        org   $0800-4
        dw $0800
        dw THE_END-THE_START
THE_START:
...
THE_END:

This works, but you are limited to the peripherals that I configure at fixed addresses.
--------------------------------------------------------------------------------------------------------
The next step would be to get the free Xilinx tools and a USB cable. Search for 'Xilinx Platform Cable USB')

Once you can flash the FPGA using the IMPACT tool, you can at the very least get FPGA binaries from me or others and modify the FPGA setup.
--------------------------------------------------------------------------------------------------------
At that point you can also look at the Verilog code and change it. You don't have to fully learn the language, you can use 'genetic engineering' techniques to tweak peripheral addresses, reassign pins, add or remove peripherals, etc.

I use a makefile to run the entire toolchain. It takes under a minute to fully recompile and reconfigure the whole circuit. Configuring the FPGA via JTAG takes a couple of seconds. Once you are happy with your configuration, it can be committed to the nonvolatile flash (using IMPACT), and the board will power up into your new circuit.

[Arlet]

To hook these up to a PC, you need a USB-TTL serial adapter. You can get them on Ebay, but the quality isn't guaranteed. I've bought 10 that were excellent, and 2 more sets of 10 that didn't work very well.

So, instead of taking another gamble, I decided to make my own.

Let me know if you're interested, and I'll sell them at cost (edit: 5 EUR) + shipping (edit: 1 EUR worldwide by regular mail) to members of this forum. They have a FT230X chip (doesn't require crystal), red/green LEDs for Rx/Tx indication, and zener diodes on the bottom to protect against ESD and latch-up. They were made for 3.3V, I have no idea if these devices are 5V tolerant.

If there's enough interest for enso's board, I could send him a few, and he can ship them together with the boards. That should save on shipping costs.

Edit: I'll take paypal (paypal fee will be added to price), bitcoin, or SEPA payment (Europe only).

[Tor]

Thanks enso and Arlet.

I'm currently researching a bit to see if I understand exactly what's needed.
At work we have a few Xilinx Platform USB Cable II, the red ones (not sure about the quality of these things, at least one of them was labelled 'does not work', and another 'this one works'. In any case there are people working with Xilinx FPGAs here at my company, just not at the moment. I can talk to them later of course).
Would one of these work until I get one for myself? I notice the II is marked '2mm connector signals' while the white ones (the one in enso's image, and some, but not all on ebay) are marked '2.54mm connector signals'. I assume this is just about the connector on the gadget itself. It connects to that JTAG connector? (I also noticed that at work we have at least one expensively-looking Xilinx gadget called 'JTAG' something).

So (assuming I'll get sorted out one way or another with the USB programmer), I guess that with (e.g.) Arlet's USB-TTL serial adapter there's a way out and in (good old serial) if the core has a serial port programmed in. On the right track so far?

-Tor

[ElEctric_EyE]

Tor wrote:

..At work we have a few Xilinx Platform USB Cable II, the red ones (not sure about the quality of these things, at least one of them was labelled 'does not work', and another 'this one works'...

I use a JTAG programmer cable I purchased from DigilentInc, now going to be just about 3 years old. Recently in my PVB project I need to program 2 separate boards independently, each with a FPGA and 2 FPGA PROMs. Over the past month, it has survived "hot-swapping" between 2 boards powered up, also an intermittent reverse plug-in!
Anyway, I see they have a newer (not necessarily better) HS2 cable for $5US more.

[ElEctric_EyE]

That's it as far as the hardware required to dive into Xilinx FPGA/CPLDs, i.e. a board with the FPGA/CPLD and a 6-pin JTAG connection to your PC...

For the software: You will need a free Xilinx ISE design suite which includes ISE iMPACT. It looks for the hardware and exports all your ISE work into some files iMPACT uses to program the FPGA/CPLD via JTAG.
You will also need your 6502 assembler that can maybe output a .bin or .hex file. Maybe others can add info here as I use 65Org16(non6502) tools kindly developed by this forum.

[enso]

Tor, I currently configure the board so that on power-up it becomes a 6502 system with a UART. Your terminal should be configured to 115.2 KBaud, no parity, 2 stop bits.

The top 2K of RAM contain a loader that displays '6502' and waits for you to send a binary over the serial port. The first two 16-bit words sent should be load address and binary size in bytes. Data should follow. As soon as all the bytes are loaded, the code is executed (at load address).

prompt.png (15.75 KiB) Viewed 22124 times

So to get started all you need is a working serial port. With it you can load FIG-FORTH, Daryl's monitor, or any 6502 code you assemble or compile.

Of course if you have any special needs besides a serial port, an 8-bit input and an 8-bit output and an LED, you should seriously consider getting a Xilinx cable. With it at the very least you will be able to get updates from me and others, even if you don't feel up to tackling more complicated tasks.

[Arlet]

Is that 45 MHz max speed number based on worst case parameters or trial and error based on typical case ? If it is by trial and error, you may need some extra safety margin when you send boards to people without a JTAG cable. It would be a shame if the boards don't run 100% reliably when used in different circumstances.

[enso]

45MHz is empirically derived. The last time I worked on the speed issue, I got to 50 and backed off to 45 for a safety margin.

I am currently testing the units before shipping, which is OK for lower volumes.

[enso]

Initial configuration
The board comes pre-configured with a 45MHz 6502 core (Arlet's) with almost 64K RAM (and some IO). The system boots into a loader on power-up. The initial configuration features
-LED output ($C000, also top left pin. Any access toggles the LED)
-UART ($C008, special pins, 115200 baud, no parity, 2 stop bits works best)
-8-bit output port ($C010, top row right side. Writing sets the bits)
-8-bit input port ($C018, bottom row, right side. Reading gets current values)
-Reset button port(2nd top pin from left)
Memory Map

Code: Select all

$0000-$01FF  BRAM
$0200-$BFFF  SRAM
$C000-$C0FF  IO
$F800-$F9FF  Mapped to $0000-$01FF
$FA00-$FFFF  BRAM, upon bootup contains loader and vectors

The mapping can be improved, but works pretty well for now. I suggest clearly isolating the IO code so that it can be changed easily - a good idea in any environment.

There is another 64K of RAM that is not currently used, and a few pins for video and SD card IO...