DRAM/SIMM refresh circuit

Bor_Ed · Post by **Bor_Ed** » Thu Apr 22, 2004 7:49 pm

I ve been trying to get some info how to get a simple dram refresh to 1 or 4 MB simm.
Google web nor groups didn't offer any usable info except getting some fpga coding and I'm not really up to that.
So, anyone made dram refresh circuity or have links to easy/cheap way to do that with commodity ttl or cmos chips ?

leeeeee · Post by **leeeeee** » Fri Apr 23, 2004 10:07 am

You don't need to bother with hardware, do it in software. All you need is to put some code in the DRAM that will cycle through every row address within the needed time.

The best code for this is something like ..

LDA #$00
LDA #$00
.
.
LDA #$00
NOP
RTS

.. as this will do the whole page in <270 cycles, then just call this as often as is needed. Also, as long as you're not running the DRAM near it's temperature limit you can stretch the refresh period to many 10s of ms so you won't lose too many cycles refreshing the DRAM

If you have 9 bit refresh SIMMs then you'll need to extend this to two pages.

IF your DRAM is part of a video circuit then you can forget refreshing completely as reading the DRAM during the video cycle will take care of it for you.

Cheers,
Lee.

Bor_Ed · Post by **Bor_Ed** » Fri Apr 23, 2004 1:01 pm

Hmm..
The whole fuzz is to avoid software refresh since 6502/816 really doesn't have spare cycles to waste imo.
The board is going to be just simple sbc without video for a starter (6502 or '816, pia/via, acia and some glue and the usual junk to put all together).
I/we have though about simple phi2 low flipflop and binary counter to go through the ram so cpu could do what's it supposed to. Shouldn't that be possible or someone done such setup ?

leeeeee · Post by **leeeeee** » Fri Apr 23, 2004 2:57 pm

Ok then you'll need a counter, preferably triggered on the +ve edge of Ø2, another input to the address multiplexers (or a tristate buffer if you use tristateable multiplexers) and either a shift register or a couple of delays to generate timing.

What you need to do is generate a read cycle but without the RAS or CAS, whichever isn't needed, and supply the counter output as the address.

It's probably easiest to get the datasheet(s) for the chips on the SIMMs you'll be using and work from those.

Cheers,
Lee.

Bor_Ed · Post by **Bor_Ed** » Fri Apr 23, 2004 3:07 pm

Thanks :)
Now we're on the same wavelenght on the approach.
Got to check out if I can locate the sheets and see if those make any sense.

John West · Post by **John West** » Fri Apr 23, 2004 4:00 pm

You haven't needed external counters for a very long time. Have a look in the datasheet for the parts that you've got. There should be something about "/CAS before /RAS refresh" or "hidden refresh". A falling edge on /RAS while /CAS is low (or something like that - it's been a long time) triggers a refresh with an internal counter. They can be hidden on the end of ordinary read cycles if you don't mind stretching the reads a little.

leeeeee · Post by **leeeeee** » Sat Apr 24, 2004 8:59 am

Yes John I realised that (after hitting submit).

The last DRAM circuit I designed from scratch used 256k x 1 chips and not all of them could do hidden refresh, in fact most couldn't.

Refresh is probably easier on the 6502 as you know you have every other half cycle free to implement it.

And no, I can't remember all the hidden refresh schemes, or any of them in detail. Guess I'll have to look up the docs again.

Cheers,

Lee.

Bor_Ed · Post by **Bor_Ed** » Sat Apr 24, 2004 3:16 pm

Lee.

You couldn't find the docs/schemas on the 256x1 refresh thingy by any change ?
Those probably won't work directly on 1 or 4 Mbit chips but gives some boost (at least I hope so) to get the circuity done.
Still waiting for sheets from the store I've been bugging about the simms...

leeeeee · Post by **leeeeee** » Sun Apr 25, 2004 8:52 am

Those diagrams were lost when one of my Amigas got hit by lightning and it fried the hard drive. There is a small chance they may be recovered, all I need is the electronics from a 4.3G SCSI Seagate Barracuda and some luck.

However I did find some DRAM datasheets that give details of the hidden refresh cycle. Try ..
http://www.austinsemiconductor.com/prod ... mj4c1024.p
.. and ..
http://www.austinsemiconductor.com/prod ... 44c256.pdf
.. or even ..
http://www.austinsemiconductor.com/prod ... m/dram.htm
.. for their DRAM page.

That should give you some ideas.

Lee.

Bor_Ed · Post by **Bor_Ed** » Sun Apr 25, 2004 1:13 pm

Hmm.
Got to try to get some idea out from the docs.
Lets see if I can get some idea how to implement the buggr.

rajsw · Post by **rajsw** » Thu May 06, 2004 9:23 pm

leeeeee wrote:

Those diagrams were lost when one of my Amigas got hit by lightning and it fried the hard drive. There is a small chance they may be recovered, all I need is the electronics from a 4.3G SCSI Seagate Barracuda and some luck.

Hey Lee,

I have a Seagate Baracuda drive, model number ST34573N which I think is the drive you are looking for. The drive works and I have no use for such a small drive. I'll be happy to send it to you for free, you just pay the shipping. I'm in Atlanta, GA (USA).

/*Raj*/

Bor_Ed · Post by **Bor_Ed** » Tue May 11, 2004 7:19 pm

Hi all.

Project to get the simm to a board is frozen currently.
National semiconductors has DP8422A dram controller which supports up to 4M x 1 bit chips, manageable to drive 8 bit simm with some buffering. Price wasn't right though and they aren't providing samples.

For that reason I turned out to maxim site and they have 2M x 8 bit sram chips DS1270Y-100 which they gladly ship as samples too, 2 of each ordered chip.
So for now I have to get along with 'only' 4 MB of free sram :)

keith · Post by **keith** » Sat Nov 13, 2004 1:54 am

http://www.howell1964.freeserve.co.uk/p ... M_6502.htm

is a simple yet effective DRAM interface for the 6502

janik · Post by **janik** » Thu Jan 27, 2005 5:28 pm

This post just to state, that this has been worked out and should be functioning correctly. Using a single 30pin SIMM with CBR (CAS-Before-RAS) refreshing scheme which tri-states the CPU by /BE during refresh cycle. Refreshing is timed by inverted CPU clock so it should not interfere with the CPU accessing the RAM nor should any wait-states or so be needed to be induced.

Thanks for the ideas thrown.

Nightmaretony · Post by **Nightmaretony** » Sat Jan 29, 2005 3:06 am

for the older TTL method, check into the Apple 2+ schematic and know how which uses 48K of dynamic ram. the GS is capacble of the SIM ram but uses customs, so its harder o the understand....