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PostPosted: Sun Jul 28, 2013 10:24 pm 
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I'm currently thinking through address decoding options for my first 6502 system, and one of the options that I'm entertaining requires driving up to about ten inputs from a single address line. Is this plausible with a "barefoot" WDC 65c02, or should I avoid (or buffer) this part of the design space?

[ Update: I found a way to get the same or better result with about half the number of inputs driven, though I am still curious about the practical maximum load for an address line. ]

-- Alastair Bridgewater


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PostPosted: Mon Jul 29, 2013 12:54 am 
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My workbench computer has eight (three VIAs, three ACIAs, RAM, and ROM), and with a 6MHz WDC 65802 and 4MHz other I/O parts and 70ns ROM (and I can't remember or see the rating on the RAM-- it might have been 55ns), it has no problems until I get over 7MHz. No buffers. WDC's drivers are very strong-- much, much stronger than the data sheet lets on, and stronger than some families' buffers you might add. 74ABT is stronger, and fast enough that there shouldn't be any penalty from their added propagation delays, but I'm not sure the net effect will give any real benefit.

CMOS inputs take no DC, being only leakage from imperfect wafer processes and usually in the picoamp or femtoamp range at room temperature, so the only real load is charging up the capacitance of those inputs and the stray capacitance of the sockets (if you use any) and the printed circuit board. If you don't use a PCB with a true ground plane, you'll have less capacitance but more inductance to work against-- the only remedy against inductance being better board layout, as stronger drivers won't help there.

The fanout limit then increases to near infinity as you drop to low clock speeds. Still, Daryl (8BIT here on the forum) has run my 4Mx8 5V 10ns SRAM module with 8 512Kx8 SRAMs, plus connectors and PCBs, plus three expansion cards, plus other things on the bus of his SBC-4P computer, at 12MHz with no buffers and no issues. How's that for drive strength? (It has a WDC 65816, which I'm sure has the same bus drivers that the 65c02 has.)

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PostPosted: Mon Jul 29, 2013 5:39 pm 
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nyef wrote:
I'm currently thinking through address decoding options for my first 6502 system, and one of the options that I'm entertaining requires driving up to about ten inputs from a single address line. Is this plausible with a "barefoot" WDC 65c02, or should I avoid (or buffer) this part of the design space?

[ Update: I found a way to get the same or better result with about half the number of inputs driven, though I am still curious about the practical maximum load for an address line. ]

-- Alastair Bridgewater

As Garth noted, there are a number of variables that make this a moving target. It's been my experience that the board layout will make the ultimate determination of maximum possible fanout. I do know that the 65C816 can drive a circuit at 15 MHz without bus drivers, as long as the layout is tight and the chip count isn't too high. Since a lot of homebrew units are built around discrete logic, it may be possible to reduce parasitic capacitance by use of programmable logic in place of individual gates.

Taking the buses off-board will incur a significant parasitic capacitance penalty, plus equally unwanted inductive effects, and is best avoided. If such a design is necessary, bus drivers and strategically placed termination resistors can help. This gets into the realm of black art, and there are experts (Dr. Howard Johnson immediately comes to mind) who have devoted years to studying this stuff.

Also, as Garth mentioned, CMOS devices present virtually no DC loading. However, current transients will occur as parasitic capacitance is charged and discharged with changes in bus state. The MPU has to provide the needed current. Therefore, the ability of the MPU to drive bus loads is affected by the robustness of the Vcc and Gnd connections, as well as by the presence (or absence) of adequate decoupling. Be sure to pay attention to these items when you do your board layout.

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PostPosted: Mon Jul 29, 2013 8:34 pm 
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Thank you both for your input. I'm still exploring the design space, and I'm not going to be able to start constructing actual hardware until the 9th at the earliest, by which point I'm hoping to have a few design options ready that I can pick and choose from based on what I can actually fit onto a single board. At the same time, I'd like to verify that my chosen design will work before I start in on permanent construction, but that can be done with a much-reduced set of I/O devices. I'm currently using and planning to use all 74HC logic for address decoding and related glue, a Twin Industries 8200-series board, and primarily wire-wrap construction.

This is getting a little bit away from the opening topic, but... other than re-reading the 6502 primer on AC performance considerations and wire-wrap construction, along with the forum topics linked from those two pages, and the sticky thread about high-speed construction techniques, is there anything else that I should be reading or keeping in mind? If I have both power and ground plane, should I still be using bypass capacitors? Given both power and ground planes, would using SMT capacitors for bypassing make sense?

[ Again partly answering my own question, http://forum.6502.org/viewtopic.php?p=8074#p8074 seems to say that I should still be using bypass caps even if I have both a power and ground plane, and specifically SMT caps, but specifies .01uF caps. Would .1uF caps also work? ]

Thank you again.

-- Alastair Bridgewater


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PostPosted: Mon Jul 29, 2013 9:26 pm 
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It sounds like you get it! I have not found very good diagrams on the web to link to to illustrate some of the concepts of what goes on at the higher frequencies, so I might have to take the time to draw some, because it seems to be difficult for many people to grasp.

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If I have both power and ground plane, [so] should I still be using bypass capacitors? Given both power and ground planes, would using SMT capacitors for bypassing make sense?

My understanding (which I would like to confirm) is that a closely spaced, infinite parallel power and ground plane pair have no inductance from one point to another, which would mean we wouldn't need a capacitor at every IC. We cannot make it infinite of course, and the negative effects are the worst as we get close to the edge of the board. Also, vias have inductance, and the foil has some skin effect. These latter two are probably too small to worry about at any frequencies you'll be confronting with off-the-shelf 65-family parts and 74HC (you might as well go to 74AC which is much faster); but adding a chip capacitor from each Vdd lead to the ground plane around it can only help, and it costs next to nothing, takes no space on the type of board you mention, and is not much labor, so why not do it. If you can make them chip capacitors (0603 or even 0402 if you have the soldering-iron tip and the steadiness for it), then do, because you don't want any extra inductance from leads. The nice thing about the proto board you mention is that with the thru-plated holes and the ground plane, you can solder one end of the capacitor to the pin and the other to the plane, and the fact that the socket pin gets soldered to the pad means that mechanical stress won't be transferred to the capacitor. You still can't get rid of the inductance from the board to the IC's die (with the socket, pin, and bondwire), but the PLCCs shorten the connection from the board to the die, and offer more ground and Vdd pins than the DIP does.

With 1-2MHz parts you can get away with murder; but you have to start paying attention to these things as you get into the higher speeds of 10-20MHz and beyond.

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specifies .01uF caps. Would .1uF caps also work?

.01 will raise the self-resonance frequency, but ideally you get rid of all the inductance so that's not an issue, and that's partly what chip capacitors are for. You cannot get rid of all of it, but chip capacitors' inductance will be sufficiently low for this purpose that Dr. Howard Johnson says there's no harm in going up to the .1's if they're in the same package size.

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is there anything else that I should be reading or keeping in mind?

Regarding construction for good AC performance? Or something else?

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PostPosted: Mon Jul 29, 2013 10:00 pm 
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nyef wrote:
Twin Industries 8200-series board, and primarily wire-wrap construction.
...
but specifies .01uF caps. Would .1uF caps also work? ]

I have used that board and it's very good for wire-wrap, just keep the wires close to the board.

I typically use .1 or .22 ceramic, I also try to spread around just few 1uf tantalum caps at various locations on the board as well.


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PostPosted: Tue Jul 30, 2013 12:50 am 
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GARTHWILSON wrote:
Quote:
is there anything else that I should be reading or keeping in mind?

Regarding construction for good AC performance? Or something else?


Construction still, yes. I should probably open another topic for further specific construction questions, though. In fact, I'll probably wait until I have a design more worked out and am closer to ready to build it on something other than a breadboard, assuming that I don't find answers in the meantime.

-- Alastair Bridgewater


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PostPosted: Tue Jul 30, 2013 6:53 am 
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clockpulse wrote:
nyef wrote:
Twin Industries 8200-series board, and primarily wire-wrap construction.
...
but specifies .01uF caps. Would .1uF caps also work? ]

I have used that board and it's very good for wire-wrap, just keep the wires close to the board.

I typically use .1 or .22 ceramic, I also try to spread around just few 1uf tantalum caps at various locations on the board as well.

On POC, I used .1 uF X7R ceramics, with a voltage rating at least 10 times that of Vcc (the reason for that ratio is somewhat esoteric). I'm not sure that the tants help all that much. Low ESR electrolytics can work just as well for general bypassing if close to a ceramic. You save some cost but sacrifice a little more board real estate. In any case, the idea is to provide a localized current source that minimizes Vcc sags when a device suddenly turns on. Also beware of ground bounce.

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PostPosted: Tue Jul 30, 2013 7:20 am 
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BigDumbDinosaur wrote:
On POC, I used .1 uF X7R ceramics, with a voltage rating at least 10 times that of Vcc (the reason for that ratio is somewhat esoteric).

EDN magazine had an article about capacitance reduction in chip capacitors starting on page 77 of the 4/12/2007 issue. The short version is to say that the capacitance begins dropping dramatically when the voltage on the capacitor exceeds about 20% of its WVDC for X7R, and much worse for Y5V. By the time you get to the WVDC, you've lost 65-70% of the capacitance for X7R. For Y5V, you've lost that much at only half the WVDC, and nearly 90% at the WVDC. The article is aimed at reducing distortion in audio circuits, but obviously it will also affect things like the frequencies of active filters; so I was glad I found the article about the time I started to do SMT designs. For the audio designs, I always use a WVDC of at least five times the DC voltage I expect to have on the capacitor, and more if it's going to get much AC voltage superimposed on it.

Quote:
I'm not sure that the tants help all that much. Low ESR electrolytics can work just as well for general bypassing if close to a ceramic.

OS-CON capacitors are much better than both low-ESR 'lytics and tantalums, and are the best thing I know of for small switching power supplies. OS-CON is a solid electrolyte type made by Sanyo and a couple of other manufacturers. They're not exactly cheap, and they only go up to 16V or 20V. Adding the X7R chip capacitors in parallel to any other type on a computer board should render the OS-CONs mostly unnecessary though.

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