Working with Xilinx BGA packages

[enso]

My 0603's fit very nicely in 1.05 mm plated holes. My boards are 1.6mm wide, leading me to believe that a cap could fit without protruding.

Measuring my caps (diagonally), I get just about 1mm. I think I will hand-drill 1mm hole to start with (0.04").

[enso]

I finally had a problem with a 700AN BGA484. The board exhibited flaky behaviour (mind you, after much reworking of other parts). In particular, flexing the board slightly caused the loss of connection on one of a dozen connected pins (I got lucky). After messing around with tests, I flexed the board hard - and the chip popped off. Most balls remained attached to the chip, although some remained attached to the board and a few edge balls grabbed traces and pulled them off the board. The balls are still round, but the bottoms are flattened a tiny bit, indicating that the melting started, but did not fully grab the pads.

I am pretty convinced the issue has to do with the surface plating. Oshpark doesn't tin-plate, but uses gold-plating, which normally is better. For this application, unfortunately, it is not ideal. I found that for hand-soldering, gold pads take a tiny bit longer before solder flows. I miss the olden days of lead and dipped boards.

I may have to go back to solderpaste (I suppose with a slightly lower melting temperature than the balls would be ideal...). I should also try a tin-plated board - I haven't done it in a while.

I baked another 700AN board, leaving it on the hotplate a little longer (visually the balls are more slumped than the last time). This time the chip is sitting lower, and the balls are slightly more barrel-shaped, indicating a better melt. The defective board has balls that are still largely round.

Lessons learned:
- Bake longer (long enough to melt the balls but not warp the board!)
- Get a stopwatch (or make a 6502-based timer, for god's sake - I have enough 6502s and FPGAs here...)
- Clean the board with alcohol or possibly acetone (I got sloppy with the last few boards)
- Try a tin-plated board from another fab
- Consider going back to using solderpaste (reluctantly - still not convinced).

[Arlet]

Maybe you can try putting a small weight (like a coin) on the chip before you heat it up to help it push down the balls.

[enso]

Arlet wrote:

Maybe you can try putting a small weight (like a coin) on the chip before you heat it up to help it push down the balls.

A common failure mode is liquifying the balls and having the chip collapse into a molten mess. The board and the chip are pretty flat (although rapid one-sided heating does warp the board a little). Maybe, although the surface of the board is my prime concern right now.

[ElEctric_EyE]

enso, like you noted about gold and higher temps... Might be worth reading the wiki on solder alloys. I think I'd read the lead free they use on the BGA solder balls is not well suited for gold surfaces. Busy at work, so I can't find the exact location I read this.

[enso]

I am pretty sure Xilinx balls are 63% tin and 37% lead on the older chips (I am using 700ANs). But yes, need to do a little more research and find a new fab.

[BigEd]

Are you using any kind of flux?

[enso]

I am using a liquid flux pen, and have been thoroughly covering the grid prior to placement. The flux smokes off pretty quickly. Anyway I do have a couple of working boards that look pretty good. I think I just rushed the one that failed. I will try to find a tin-plated board fab next.

[BigEd]

Sound like careful timing of the temperature profile is crucial. Slow ramp, to minimise thermal stress, short plateau just at the melting point to get the result, then ramp down before it all goes gooey and overcooked. A setup with a PIR controller is already part-way to an automated profile.

[enso]

Last night I drilled a board for embedding capacitors. I had a 1.05mm bit - that worked fine. The cap fits OK and hand-soldering is not a problem as long as you feed enough solder to make a little ball over it. Then, the other side.

However I was hoping to keep the solder joint flat enough to put a qfp over it. No such luck. Removing solder with a wick takes too much off and provides little control. Not applying enough solder is hard too - the pad just won't get wet (even with flux) unless a whole bunch of solder trips the process. Gold-plated boards, again. Tinning the pad before helps, but then it's hard to stick in the cap.

Overall I find the experience too hard to be that useful. I was hoping it would be possible to just apply paste over the cap, but I doubt it will work consistently enough to not have to check every cap with a microscope... I will try pasting over a few caps later.

One of the main reasons I tried it is to avoid putting anything on the backside of the board, for the hotplate. I should get the oven control working I suppose.

[ElEctric_EyE]

I tried experimenting today with a board from the garage. I keep old parts around, it was a 2"x4" board with 2 QFPs and a 15mmx15mm BGA with .8mm spacing (just a few vias underneath). With a temp setting of 250C, the board never got above 190C avg in the lower region. This board had a thru-hole connector which did raise it off of the hotplate by more than 1mm at that edge. Temps were 110C in that region and nothing was able to be removed
250C seems to be a good temp for this hotplate, there is just a bit of smoke now and then but the board doesn't seem to get burnt, even after about 20 mins, including ramp up.

EDIT: On another board with similar connector conditions which made the board unlevel, I ramped up the temps to 270C. Smoke was pretty much constant, but the board seemed unburnt after 20 min's. This is going to be my last demounting experiment... Pb smoke does wind up doing some nervous system damage over time, and I don't need this problem.

[ElEctric_EyE]

So I was working some on my BGA layout the past couple days.
This BGA soldering experiment may wind up being an absolute failure, in which case I will have to switch board manufacturers, because this is all I can do with a 4 layer board with the current design tools.
23 signal pins were wasted, i.e non-routable through the top or bottom layers. I concentrated on getting most of the GCLKs out. Most of them are on the upper right quarter of the device.
161 signals I have to work with. Could be maybe more, but I dont like using JTAG signal pins as multifunction. My current level of success I keep all JTAG pins as dedicated.
VDD pins marked in the pic below include all VCCint, VCCaux and VCCO.
I've tested this EPCB layout file, and it was accepted, so I'm not breaking any of the layout rules.
The next step is to choose and route a serial FLASH in order to program the FPGA. Also, the internal power and ground layers still need to be divided under the FPGA template.

[enso]

What are the smallest drills and annular ring sizes your fab allows?

EDIT: I am confused over where the vias are

[ElEctric_EyE]

enso wrote:

What are the smallest drills and annular ring sizes your fab allows?

EDIT: I am confused over where the vias are

The smallest is: .026" with .008" hole. That is what I'm using.

Maybe the silkscreen makes it difficult to see. I just used it to label the pins to make it easier to check. I'll post a pic without silkscreen.
The green layer is the bottom layer. The 2 inner layers are not shown, they still need work.

[GARTHWILSON]

Quote:

The smallest is: .026" with .008" hole. That is what I'm using.

I definitely would not go with an .008" hole in .062" PCB, as that's well beyond the 4:1 ratio of hole length to diameter limit where the thru-plating is reliable. Are you using .032" PCB? If not, you will need to check with the PCB manufacturer to ask about their capabilities in this area. (I would be delighted to find out that they can now commonly and reliably do an 8:1 length-to-diameter ratio!) It only takes one bad one on a board to give you a lot of grief.

The .032"-thick PCB should be plenty strong for small boards and will give better AC performance too if it's just two layers and one is mostly ground plane, as two adjacent traces on the signal side will talk to each other less if the ground plane is closer because the board is thinner.