... you could try pulling off the FPGA and analyze the damage to see how they were soldered.
I may have to resort to this. I have a couple of 200ANs off the boards from previous attempts, having to do with solderpaste application.
ElectricEyE- Thanks for the schematic pointer. I will refer to it and check the wiring. These boards usually have way too many devices connected, but should be helpful anyway.
Possible explanation
Because my circuit is a 2-layer board, I routed some power and ground buses directly across unused IO pins deep inside the grid, thinking that it should not matter. At some later point I think I grounded the PUDC_B pin, enabling internal pullup resistors during configuration (I can't remember why I did this). This, of course, turnes the grounded pins and their respective pullups into little heaters.
If this is the case, the boards are actually usable since the heating is not terminal and the issue should go away after configuration, which should not take more than a few seconds.
Is the 0.8A current consumption consistent with 10-20 shorted IO pins? It seems a little high, but well within the range of possible. I am away from the circuit, will check this later today.
Edit: looking at the layout I counted 49 inner pins that are grounded by the power distribution bus. With a meter, 3.3V power grid draws approximately 730mA. That's about 15mA per pin, perfectly explaining the problem.
Next task: create a simple test circuit and configure the FPGA, which should fix the problem...
