Over here in a thread about the 65816 WhiteFlame mentioned the SuperCPU and this board photo:

Attachment:

(There's some general product info here)

BDD pointed out


I note that the above board and other boards on nearby pages have GALs on them, and the more complex boards also use CPLDs.

Here are the related pages nearby:
CMD SUPER CPU - Tools
CMD SUPER CPU - Games
SUPER CPU's - History
HOW TO: Fix Games to work on SUPER CPU
SUPER CPU 64 - Look Inside (the page behind the photo above)
SUPER CPU 128- Look Inside

There's a long thread on lemon64 which mentions that the GALs have been dumped and the schematics reversed.

There's a pdf here about a RAM expansion which goes into a little detail about clock-stretching on the SuperCPU (it's a 20MHz CPU on a 1MHz machine, so something must be done for off-board devices!)

There's a user guide here for the RAM expansion which tells us that the two connectors near the North edge are for that purpose.

The V2 board (user guide) had 5 microclips which connect to the host machine's CPU - a bit more invasive.

Cheers
Ed

Found a clearer picture (of a different board...) on the lemon64 thread:

From what I recall, all SCPU 65816s are overclocked 14MHz parts.

The pins in the upper left go to an optional memory expansion board which takes SIMM sticks. Luckily, those were still (barely) available for cheap when I got mine, and have 16MB in there.

The memory interface to the C64's bus buffers 1 memory write at a time, so you're not that bandwidth limited for controlling the original hardware. Since it's a stock 816 and that uses an 8-bit data bus, I'd suspect the buffer is only 8 bits and that a 16-bit write to the main system would always block waiting for the second byte to buffer.

Reads from the C64's memory space of course must wait for a round trip through the 1MHz bus.

_________________
WFDis Interactive 6502 Disassembler
AcheronVM: A Reconfigurable 16-bit Virtual CPU for the 6502 Microprocessor

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

Yeah, none of the bandwidth issues come into play for much of the CPU-bound coding, as the host C64 basically becomes nothing more than an I/O device.

_________________
WFDis Interactive 6502 Disassembler
AcheronVM: A Reconfigurable 16-bit Virtual CPU for the 6502 Microprocessor

I wasn't sure if there was a request for information in this thread, but I was around during the development of this unit and remember some about it, if there's a question. I also have a unit or so here.

The internal board with the clips was only needed for C128 use. C64 use did not require the board. The board was to make up for a lack of knowledge of the internal C128 MMU from the expansion port.

The 4 RAMs (128kB) there held 64kB of RAM and a shadow copy of the ROMs, since the ROM did not run fast enough. As others have noted, the 6510 was tristated and the system just used the bus in reverse. You could configure how much of the RAM space to "mirror" inside the 64. As noted, a single write to IO would not slow it down, but a second in 20 cycles would stretch the clock out to allow the previous write to complete.

I was not aware WSG sold -20 parts. Doug Cotton of CMD always noted that they were told by Bill that the -14 was the fastest marking, but that they would do 20 with no issues, so -14's were purchased for the units.

Jim

Thanks for the offer of info Jim. My aim with this thread was to collect and concentrate knowledge about this successful 816 product.

(Datasheet for the RAM chips at http://www.alliancememory.com/pdf/sram/ ... av.1.2.pdf, although it's not especially useful)

Cheers
Ed

Here are two illustrations from the PDF I linked to in the head post:

Been having a look at this recently. It has me wondering, how did they manage to get this working entirely through the cartridge port? Because the ports P0 to P5 (on the 6510) aren't accessible through the cartridge port.

Port 0 to 2 being of high importance.

P0 - LORAM
P1 - HIRAM
P2 - CHAREN





Pretty much everything else required is on the cartridge port to run a CPU externally except for the ports.

Any idea how they got around this, without having to modify the innards of the C64?

It has me intrigued!

Locations 0 and 1 are virtual on the CPU (mapping to P0 to P5), so these would just write to the 65816, and it would just set the lines as required.

I also guess worst case, they could have the CPLD page in the CPU "just" to set those lines...

Hi Mike,

Thanks for the reply.

That's the thing, the 65816 can't set he port lines from the expansion port side. I have since found out that all of the kernal and and control logic are replicated on the SuperCPU board, so the PLA (where the 6510 ports normally direct to) is sitting in its default state. So this pretty much answers my own question really.