Thank you both! I was going to ask Arlet the following, but I think I've found my problem, in the middle of posting, in the opcode decoding for the adc_sbc flag.
In your core, when it executes any opcode that sets the OP_SUB flag for the ALU.v to do a subtraction, in which the ALU would have to change the C flag going back into the cpu, I don't see how that CO signal works it way back into the cpu.v for the OP_SUB opcodes.
Code: Select all
/*
* Update C flag when doing ADC/SBC, shift/rotate, compare
*/
always @(posedge clk )
if( shift && state == WRITE )
C <= CO;
else if( state == RTI2 )
C <= DIMUX[0];
else if( ~write_back && state == DECODE ) begin
if( adc_sbc | shift | compare )
C <= CO;
else if( plp )
C <= ADD[0];
else begin
if( sec ) C <= 1;
if( clc ) C <= 0;
end
end
The adc_sbc is for the addition opcodes
EDIT: In comparing the 2 cores, I think I just saw my error. One I think I've had from the very beginning of tinkering with Verilog and your core. I had misunderstood your adc_sbc flag to be set for
only the ADC opcodes, which I always thought was strange. Which now I see it is strange, because it's wrong.
