Weird JMP problem

[BigEd]

Or indeed, as we've said before, you want an adequately fast rise and fall time on the clock. Your hyperbole does not always improve your message, BDD.
Cheers
Ed

[Mercury1964]

Just tried the 74HC14. Works possibly a little better, but still conks out when I wait longer than a few seconds between cycles.

[Dr Jefyll]

Mercury1964 wrote:

... but still conks out when I wait longer than a few seconds between cycles.

That's twice you've remarked on the delay aspect. One possible explanation for the effect is that you have an error in the logic that enables the memory chip, and that it is being enabled during the period when PHI2 is low rather than when PHI2 is high. In that case the data would appear earlier than required. Because there's some capacitance present, the data could conceivably remain valid, stored by the capacitance, for several seconds even after the memory IC is disabled. But it's an unreliable phenomenon; eventually the voltages would drift to meaningless values.

Dunno if that explanation is helpful for you, but at any rate the question is this: what sort of logic do you have connected to the Chip Enable and Output Enable of the memory chip? You need both of those inputs to be active (ie, low) during the PHI2 high period of a Read cycle.

cheers,
Jeff

[Mercury1964]

It's a SPDT switch, shared between PHI2 and a button connected to ground. I'll try disconnecting the switch and directly connecting PHI2 to the OE and CE lines of the RAM.

[GARTHWILSON]

Quote:

I'll try disconnecting the switch and directly connecting PHI2 to the OE and CE lines of the RAM.

These lines of the RAM are negative logic, so they will have to be low when phase 2 is high.

[Dr Jefyll]

GARTHWILSON wrote:

These lines of the RAM are negative logic, so they will have to be low when phase 2 is high.

Right. One simple solution is to connect PHI2 and R/W to the inputs of a NAND gate (eg: 74hc00) and connect the output of the NAND gate to OE of the memory. CE can simply be grounded, for now at least, since you have no other memory or IO devices on the bus. The setup for your experiment can be simpler than what an actual, functional system would use.

I don't know what to say about WE because I don't understand how you're loading your test code into the RAM. Obviously it has to get written somehow, so we can't consider WE "unused" and just tie it high (ie, inactive).

On the bright side, I think we've explained the delay effect you mentioned, and perhaps some other symptoms as well. Seems like you need to focus your attention on what the various control lines (PHI2, WE, RE etc) do. Also be aware that, in some cases, a logic high indicates True or Active; in other cases (as with OE and WE) a logic high calls for False or Inactive. If you have any more questions it will be very helpful if you supply a diagram of your circuit.

cheers,
Jeff

[Mercury1964]

Okay. I'm about 70% done with the new schematic, I'll upload it in a bit.

[GARTHWILSON]

Any progress?

[Mercury1964]

Almost. I've been pretty busy with schoolwork over the past week, but I'll upload them after I finish the clock signal generator.
Is Eeschema format okay?

[GARTHWILSON]

Quote:

Is Eeschema format okay?

It sounds like schematic CAD. I've never heard of it, but anything you can make an image from to post is fine. Posting an Eeschema file directly probably won't work, but it should be easy to get a screen shot if necessary to get an image file.